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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5606S Rev. 6, 26 Jan 2011
MPC5606S
MPC5606S Microcontroller Data Sheet
LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm)
* High performance 64 MHz e200z0h CPU - 32-bit Power Architecture(R) technology CPU - Up to 60 DMIPs operation - Variable length encoding (VLE) * Memory available - Up to 1 MB on-chip flash memory, with ECC - Up to 48 KB on-chip SRAM with ECC - 160 KB on-chip graphic SRAM - External flash extension via QuadSPI - 12-entry memory protection unit * Dashboard peripheral set - 6 stepper motor drivers with stall detection and zero positioning - 4 40 or 6 38 LCD display driver - Sound control - Real-time clock * TFT display control unit - 4 plane and cursor graphic controller - Display capable of driving up to WVGA - 24-bit RGB - Parallel Data Interface * Interrupts and DMA - Up to 128 selectable interrupts - 16 priority levels - Non-maskable interrupt (NMI) - Up to 32 external interrupts with 18 wakeup lines - 16-channel eDMA controller * Up to 133 GPIOs in LQFP176 * Timer units - 4-channel 32-bit periodic interrupt timers - 4-channel 32-bit system timer module - System watchdog timer * Timed I/O - 8-channel 16-bit counter IC/OC - 16-channel 16-bit counter IC/OC/PWM * Communications interface - 2 FlexCAN interfaces (2.0B active)
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- Up to 3 LINFlex/UART channels - Up to 3 DSPI channels, with one Quad-SPI - Up to 4 I2C interfaces 16/23-channel, 10-bit analog-to-digital converter On-chip CAN/UART bootstrap loader Clock generation - 4-16 MHz fast external crystal oscillator - 32 KHz slow external crystal oscillator - 16 MHz fast internal RC oscillator - 128 kHz slow internal RC oscillator for low power modes - Up to 2 software-controlled internal FMPLL modulated or not Exhaustive debugging capability - Nexus L1 on all devices - Nexus L2+ on LBGA208 package - Nexus L2+ on LQFP176 package as alternate function Voltage supply - Single 5 V or 3.3 V supply for I/Os and ADC - On-chip voltage regulator with external ballast transistor Operating temperature range 40 to 105 C
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2009-2011. All rights reserved.
Table of Contents
1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.4 MPC5606S series blocks . . . . . . . . . . . . . . . . . . . . . . . .4 1.5 MPC5606S features . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.6 Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pinout and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . .24 2.1 144 LQFP package pinouts . . . . . . . . . . . . . . . . . . . . .24 2.2 176 LQFP package pinout . . . . . . . . . . . . . . . . . . . . . .28 2.3 208 MAPBGA package ballmap . . . . . . . . . . . . . . . . . .29 2.4 Pad configuration during reset phases . . . . . . . . . . . . .30 2.5 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.6 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.7 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.8 Debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.9 Port pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .55 3.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .57 3.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .62 3.6 Electromagnetic compatibility (EMC) characteristics . .64 3.7 3.8 3.9 3.10 3.11 Power management electrical characteristics . . . . . . . 66 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . 74 SSD specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 RESET electrical characteristics . . . . . . . . . . . . . . . . . 83 Fast external crystal oscillator (4-16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 86 3.12 Slow external crystal oscillator (32 KHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 88 3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 90 3.14 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 91 3.15 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 91 3.16 Flash memory electrical characteristics . . . . . . . . . . . 92 3.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 93 3.18 LCD driver electrical characteristics . . . . . . . . . . . . . 100 3.19 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . 100 3.20 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.1 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.2 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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MPC5606S Microcontroller Data Sheet, Rev. 6 2 Freescale Semiconductor
1
1.1
Overview
Document overview
This document describes the device features and highlights important electrical and physical characteristics. For functional characteristics, see the MPC5606S Microcontroller Reference Manual.
1.2
Description
The MPC5606S family of chips is designed to enable the development of automotive instrument cluster applications by providing a single-chip solution capable of hosting real-time applications and driving a TFT display directly using an on-chip color TFT display controller. MPC5606S chips incorporate a cost-efficient host processor core compliant with the Power Architecture(R) embedded category. The processor is 100% user-mode compatible with the Power Architecture and capitalizes on the available development infrastructure of current Power Architecture devices with full support from available software drivers, operating systems and configuration code to assist with users' implementations. Offering high performance processing at speeds up to 64 MHz, the MPC5606S family is optimized for low power consumption and supports a range of on-chip SRAM and internal flash memory sizes. The version with 1 MB of flash memory (MPC5606S) features 160 KB of on-chip graphics SRAM. See Table 1 for specific memory and feature sets of the product family members.
1.3
Device comparison
Table 1. MPC5606S family device comparison
Feature CPU Execution speed Flash memory (ECC) EEPROM Emulation Block (ECC) SRAM (ECC) Graphics SRAM MPU eDMA Display Control Unit (DCU) Parallel Data Interface Stepper Motor Controller (SMC) Stepper Stall Detect (SSD) Sound Generation Logic (SGL) LCD driver 32 KHz slow external crystal oscillator No No 24 KB No 256 KB MPC5602S MPC5604S e200z0h Static - 64 MHz 512 KB 4 x 16 KB 48 KB No 12 entry 16 channels No No 6 motors Yes Yes 40 x 4, 38 x 61 Yes Yes Yes 48 KB 160 KB 1 MB MPC5606S
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 3
Table 1. MPC5606S family device comparison (continued)
Feature Real-Time Counter and Autonomous Periodic Interrupt Periodic Interrupt Timer (PIT) Software Watchdog Timer (SWT) System Timer Module (STM) Timed I/O2 MPC5602S Yes MPC5604S Yes 4 ch, 32-bit Yes 4 ch, 32-bit 8 ch, 16-bit IC/OC 16 ch, 16-bit OPWM/IC/OC3 ADC4 CAN (64 mailboxes) CAN sampler SCI SPI QuadSPI serial flash interface I2C GPIO Debug Package 2 x DSPI No 2 105 Nexus 1 144 LQFP 1 x FlexCAN 16 channels, 10-bit 2 x FlexCAN Yes 2 x LINFlex 2 x DSPI No 2 105 Nexus 1 144 LQFP 35 x DSPI Yes 4 105 (144-pin package) 133 (176-pin package) Nexus 2+6 144 LQFP7 176 LQFP 208 MAPBGA8 2 x FlexCAN MPC5606S Yes
1 2 3 4 5 6 7 8
Configuration is software-programmable. IC-Input Capture, OC-Output Compare, OPWM-Output Pulse Width Modulation. This functionality is split over two eMIOS blocks. Support for external multiplexer enabling up to 23 channels. QuadSPI serial Flash controller can be optionally used as a third DSPI. Nexus2+ available on 176 LQFP as alternate pin function and on 208 MAPBGA. Not all features are available simultaneously in 144 LQFP package option. The 208-pin package is not a production package; it is available in limited quantities for tool development only.
1.4
1.4.1
MPC5606S series blocks
Block diagram
Figure 1 shows a high-level block diagram of the MPC5606S series.
MPC5606S Microcontroller Data Sheet, Rev. 6 4 Freescale Semiconductor
NMI
Nexus Port
JTAG Port Video SRAM
SRAM Test Controller
Flash
Nexus Port Controller
JTAG
SRAM Controller
Flash Controller
SRAM Controller
FIRC 16 MHz SIRC 128 kHz XTAL/ EXTAL XTAL32/ EXTAL32 FXOSC 4-16 MHz SXOSC 32 KHz 2x FMPLL Clock Monitor Unit (CMU)
NMI SIU
Instructions e200z0h Data 4 x 4 32-bit Crossbar Switch Nexus 2+ MPU (Memory Protection Unit)
Voltage Regulator DMA External Interrupts from Peripheral Blocks Interrupt Controller (INTC) DCU
QuadSPI
Data and Clock
RGB TFT Output Parallel Data Interface (PDI) 40 x 4 LCD
speaker/ buzzer
Sound Generation Logic RTC/ API
STM
4 x PIT
SSCM Mode Entry Module
Power Control Unit
Clock Generation Module
SWT
BAM
Reset Generation Module
LCD FP and BP signals
Peripheral Bridge
SIU External Interrupts Reset Control External Interrupt Request IMUX GPIO & Pad Control 16 ch. 10-bit ADC
Six Gauge Drivers with Stepper Stall Detect (SSD)
2x eMIOS 16 + 8 ch.
2x LINFlex
2x DSPI
4 x I 2C
2x FlexCAN
I/O
...
...
...
...
...
...
Figure 1. MPC5606S series block diagram
1.5
1.5.1
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MPC5606S features
Summary
Single issue, 32-bit Power Architecture technology compliant CPU core complex (e200z0h) -- Compatible with Power Architecture instruction set
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 5
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-- Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional Book E compliant code On-chip ECC flash memory with flash controller -- Up to 1 MB primary flash--two 512 KB modules with prefetch buffer and 128-bit data access port -- 64 KB data flash--separate 416 KB flash block for EEPROM emulation with prefetch buffer and 128-bit data access port Up to 48 KB on-chip ECC SRAM with SRAM controller Up to 160 KB on-chip non-ECC graphics SRAM with SRAM controller Memory Protection Unit (MPU) with up to 12 region descriptors and 32-byte region granularity to provide basic memory access permission Interrupt Controller (INTC) with up to 127 peripheral interrupt sources and eight software interrupts 2 Frequency-Modulated Phase-Locked Loops (FMPLLs) -- Primary FMPLL provides a 64 MHz system clock -- Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus masters (AMBA 2.0 v6 AHB) 16-channel Enhanced Direct Memory Access controller (eDMA) with multiple transfer request sources using a DMA channel multiplexer Boot Assist Module (BAM) supports internal flash programming via a serial link (FlexCAN or LINFlex) Display Control Unit to drive TFT LCD displays -- Includes processing of up to four planes that can be blended together -- Offers a direct unbuffered hardware bit-blitter of up to 16 software-configurable dynamic layers in order to drastically minimize graphic memory requirements and provide fast animations -- Programmable display resolutions are available up to WVGA Parallel Data Interface (PDI) for digital video input LCD segment driver module with two software programmable configurations: -- Up to 40 frontplane drivers and 4 backplane drivers -- Up to 38 frontplane drivers and 6 backplane drivers Stepper Motor Controller (SMC) module with high-current drivers for up to six instrument cluster gauges driven in full dual H-Bridge configuration including full diagnostics for short circuit detection Stepper motor return-to-zero and stall detection module Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and polyphonic sound 24 eMIOS channels providing up to 16 PWM and 24 input capture / output compare channels 10-bit Analog-to-Digital Converter (ADC) -- Maximum conversion time of 1 s -- Up to 16 internal channels, expandable to 23 via external multiplexing Up to 2 Deserial Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous, communications with external devices (extendable to include up to 8 multiplexed external channels) QuadSPI serial flash memory controller supporting single, dual and quad modes of operation to interface to external serial flash memory. QuadSPI can be configured to function as another DSPI module (MPC5606S only). 2 Local Interconnect Network Flexible (LINFlex) controller modules capable of autonomous message handling (master), autonomous header handling (slave mode), and UART support. Compliant with LIN protocol rev 2.1 2 full CAN 2.0B controllers with 64 configurable buffers each; bit rate programmable up to 1 Mbit/s Up to 4 Inter-integrated circuit (I2C) internal bus controllers with master/slave bus interface Up to 133 configurable general purpose pins supporting input and output operations
MPC5606S Microcontroller Data Sheet, Rev. 6
6
Freescale Semiconductor
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Real Time Counter (RTC) with multiple clock sources: -- 128 kHz slow internal RC oscillator or 16 MHz fast internal RC oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds -- 32 KHz slow external crystal oscillator, supporting wakeup with 1 s resolution and maximum timeout of one hour -- 4-16 MHz fast external crystal oscillator System timers: -- 4-channel 32-bit System Timer Module (STM)--included in processor platform -- 4-channel 32-bit Periodic Interrupt Timer (PIT) module -- Software Watchdog Timer (SWT) System Integration Unit (SIU) module to manage resets, external interrupts, GPIO and pad control System Status and Configuration Module (SSCM) to provide information for identification of the device, last boot mode, or debug status and provides an entry point for the censorship password mechanism Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface, enabling access to all clock sources Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and act as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock Mode Entry Module (MC_ME) to control the device power mode, i.e., RUN, HALT, STOP, or STANDBY, control mode transition sequences, and manage the power control, voltage regulator, clock generation and clock management modules Reset Generation Module (MC_RGM) to manage reset assertion and release to the device at initial power-up Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) On-chip voltage regulator controller for regulating the 3.3 or 5 V supply voltage down to 1.2 V for core logic (requires external ballast transistor) The MPC5606S microcontrollers are offered in the following packages:1 -- 144 LQFP, 0.5 mm pitch, 20 mm 20 mm outline -- 176 LQFP, 0.5 mm pitch, 24 mm 24 mm outline -- 208 MAPBGA, 1.0 mm pitch, 17 mm 17 mm outline (not a production package; available in limited quantities for tool development only)
1.6
1.6.1
Details
Low-power operation
MPC5606S devices are designed for optimized low-power operation and dynamic power management of the core processor and peripherals. Power management features include software-controlled clock gating of peripherals and multiple power domains to minimize leakage in low-power modes. There are two static low-power modes, STANDBY and STOP, and two dynamic power modes--RUN and HALT. Both low power modes use clock gating to halt the clock for all or part of the device. The STANDBY mode also uses power gating to automatically turn off the power supply to parts of the device to minimize leakage. STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption mode. The contents of the cores, on-chip peripheral registers and potentially some of the volatile memory are lost. STANDBY mode is configurable to make certain features available with the disadvantage that these consume additional current: * It is possible to retain the contents of the full RAM or only 8 KB.
1. See the device comparison table or orderable parts summary for package offerings for each device in the family.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 7
* *
It is possible to enable the internal 16 MHz or 128 kHz RC oscillator, the external 4-16 MHz oscillator, or the external 32 KHz oscillator. It is possible to keep the LCD module active.
The device can be awakened from STANDBY mode via from any of up to 19 I/O pins, a reset or from a periodic wake-up using a low power oscillator. STOP mode maintains power to the entire device allowing the retention of all on-chip registers and memory, and providing a faster recovery low power mode than the lowest STANDBY mode. There is no need to reconfigure the device before executing code. The clocks to the core and peripherals are halted and can be optionally stopped to the oscillator or PLL at the expense of a slower start-up time. STOP is entered from RUN mode only. Wake-up from STOP mode is triggered by an external event or by the internal periodic wake-up, if enabled. RUN modes are the main operating mode where the entire device can be powered and clocked and from which most processing activity is done. Four dynamic RUN modes are supported--RUN0 - RUN3. The ability to configure and select different RUN modes enables different clocks and power configurations to be supported with respect to each other and to allow switching between different operating conditions. The necessary peripherals, clock sources, clock speed and system clock prescalers can be independently configured for each of the four RUN modes of the device. HALT mode is a reduced activity, low power mode intended for moderate periods of lower processing activity. In this mode the core system clocks are stopped but user-selected peripheral tasks can continue to run. It can be configured to provide more efficient power management features (switch-off PLL, flash memory, main regulator, etc.) at the cost of longer wake up latency. The system returns to RUN mode as soon as an event or interrupt is pending.
MPC5606S Microcontroller Data Sheet, Rev. 6 8 Freescale Semiconductor
Table 2 summarizes the operating modes of MPC5606S devices. Table 2. Operating mode summary1
Operating modes: SoC features Core Peripherals Flash memory SRAM Graphics RAM Clock sources Main PLL Auxiliary PLL 16 MHz IRC X OSC 128 kHz IRC 32 KHz XOSC Periodic Wake-up Wake-up input VREG mode Wakeup times5 VREG start-up IRC wake-up Flash memory recovery OSC stabilization PLL lock S/W reconfig Mode switch over
1
RUN On OP OP On On OP OP On OP On OP -- -- FP -- -- -- -- -- -- --
HALT CG OP OP On On OP OP On OP On OP OP OP FP -- -- -- -- -- -- TBD
STOP CG CG CG CG CG CG CG OP OP On OP OP OP LP 50 s 4 s 20 s 1 ms 200 s -- 24 s
STANDBY Off Off
2
POR -- -- -- -- -- -- -- -- -- -- -- -- -- -- 250 s6 8 s 100 s 1 ms 200 s -- BAM
Off Off Off 8 KB4 Off Off Off OP OP On OP OP OP LP 50 s 8 s 100 s 1 ms 200 s Var 28 s
Off CG
3
Off Off Off OP OP On OP OP OP LP 250 s 4 s 100 s 1 ms 200 s Var 28 s
Table Key: On- Powered and clocked OP- Optionally configurable to be enabled or disabled (clock gated) CG- Clock Gated, Powered but clock stopped Off- Powered off and clock gated FP- VREG Full Performance mode LP- VREG Low Power mode, reduced output capability of VREG but lower power consumption Var- Variable duration, based on the required reconfiguration and execution clock speed BAM- Boot Assist Module Software and Hardware used for device start-up and configuration 2 The LCD can optionally be kept running while the device is in STANDBY mode 3 All of the RAM content is retained, but not accessible in STANDBY mode 4 8 KB of the RAM content is retained, but not accessible in STANDBY mode
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 9
5
A high level summary of some key durations that need to be considered when recovering from low power modes. This does not account for all durations at wake up. Other delays will be necessary to consider including, but not limited to the external supply start-up time. IRC Wake-up time must not be added to the overall wake-up time as it starts in parallel with the VREG. All other wake-up times must be added to determine the total start-up time 6 This is the startup of the regulator that happens after the 5 V has reached beyond its POR range. If the external supply ramp rate is slow, measure from when VREG has crossed beyond the POR threshold, otherwise this value will depend on the ramp rate of the external supply (VDDR).
Additional notes on low power operation: * * Fast wake-up using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM on exit from low power modes The 16 MHz internal RC oscillator supports low speed code execution and clocking of peripherals when it is selected as the system clock and can also be used as the PLL input clock source to provide fast start-up without the external oscillator delay MPC5606S devices include an internal voltage regulator that includes the following features: -- Regulates input to generate all internal supplies -- Manages power gating -- Low power regulators support operation when in STOP and STANDBY modes to minimize power consumption -- Startup on-chip regulators in <50 s for rapid exit of STOP and STANDBY modes -- Low voltage detection on main supply and 1.2 V regulated supplies
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1.6.2
e200z0h core processor
The e200z0h processor is similar to other processors in the e200zx series but supports only the VLE instruction set and does not include the signal processing extension for DSP applications or a floating point unit. The e200z0h has all the features of the e200z0 plus: * * Branch acceleration using Branch Target Buffer (BTB) Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory via independent Instruction and Data BIUs
The e200z0h processor uses a four stage in-order pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), an 832 Hardware Multiplier array, result feed-forward hardware, and a hardware divider. Most arithmetic and logical operations are executed in a single cycle with the exception of the divide and multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Branch target prefetching from the BTB is performed to accelerate certain taken branches. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into an instruction buffer capable of holding four instructions. Conditional branches not taken execute in a single clock. Branches with successful target prefetching have an effective execution time of one clock on e200z0h. All other taken branches have an execution time of two clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The
MPC5606S Microcontroller Data Sheet, Rev. 6 10 Freescale Semiconductor
load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases. The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. Vectored and autovectored interrupts are supported. Hardware vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This allows the Power Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16-bit and 32-bit instructions. This results in a significantly smaller code size footprint without affecting performance noticeably. The CPU core is enhanced by an additional interrupt source--Non Maskable Interrupt. This interrupt source is routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing the Interrupt Controller completely. Once the edge detection logic is programmed, it can not be disabled, except by reset. The Non Maskable Interrupt is, as the name suggests, completely un-maskable and when asserted will always result in the immediate execution of the respective interrupt service routine. The Non maskable interrupt is not guaranteed to be recoverable. The CPU core has an additional `Wait for Interrupt' instruction that is used in conjunction with low power STOP mode. When Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt. Additional features include: * Load/store unit -- 1-cycle load latency -- Misaligned access support -- No load-to-use pipeline bubbles Thirty-two 32-bit general purpose registers (GPRs) Separate instruction bus and load/store bus Harvard architecture Reservation instructions for implementing read-modify-write constructs Multi-cycle divide (divw) and load multiple (lmw) store multiple (smw) multiple class instructions, can be interrupted to prevent increases in interrupt latency Extensive system development support through Nexus debug port
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1.6.3
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and four slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width. The crossbar allows four concurrent transactions to occur from any master port to any slave port but one of those transfers must be an instruction fetch from internal flash. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters having equal priority are granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features: * 4 master ports: -- e200z0h core instruction port -- e200z0h core complex load/store data port -- eDMA controller -- Display control unit
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 11
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4 slave ports: -- 1 flash port dedicated to the CPU -- Platform SRAM -- QuadSPI serial flash controller -- 1 slave port combining: - Flash port dedicated to the Display Control Unit and eDMA module - Graphics SRAM - Peripheral bridge 32-bit internal address bus, 32-bit internal data bus
1.6.4
Enhanced Direct Memory Access (eDMA)
The eDMA module is a controller capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA module provides the following features: * * * * * * * 16 channels support independent 8-, 16- or 32-bit single value or block transfers Supports variable sized queues and circular queues Source and destination address registers are independently configured to post-increment or remain constant Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer DMA transfers possible between system memories, QuadSPI, DSPIs, I2C, ADC, eMIOS and General Purpose I/Os (GPIOs) Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA channel with up to a total of 64 potential request sources.
1.6.5
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Inter-IC communications module (I2C)
Up to four I2C modules supported Two-wire bi-directional serial bus for on-board communications Compatibility with I2C bus standard Multimaster operation Software-programmable for one of 256 different serial clock frequencies Software-selectable acknowledge bit Interrupt-driven, byte-by-byte data transfer Arbitration-lost interrupt with automatic mode switching from master to slave Calling address identification interrupt Start and stop signal generation/detection Repeated START signal generation Acknowledge bit generation/detection Bus-busy detection
The I2C module features the following:
MPC5606S Microcontroller Data Sheet, Rev. 6 12 Freescale Semiconductor
1.6.6
Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. Multiple processors can assert interrupt requests to each other through software setable interrupt requests. These same software setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a software setable interrupt request to finish the servicing in a lower priority ISR. Therefore these software setable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following features: * * * * * * Unique 9-bit vector for each of the possible 128 separate interrupt sources 8 software triggerable interrupt sources 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source Ability to modify the ISR or task priority. -- Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources. External non maskable interrupt directly accessing the main core critical interrupt mechanism 32 external interrupts
1.6.7
QuadSPI serial flash controller
The QuadSPI module enables use of external serial flash memories supporting single, dual and quad modes of operation. It features the following: * * * * * Memory mapping of external serial flash Automatic serial flash read command generation by CPU, DMA or DCU read access on AHB bus Supports single, dual and quad serial flash read commands Flexible buffering scheme to maximize read bandwidth of serial flash `Legacy' mode allowing QuadSPI to be used as a standard DSPI (no DSI or CSI mode)
1.6.8
System Integration Unit (SIU)
The SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The GPIO features the following: * * * * Up to 4 levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of device functions for each package Centralized general purpose input output (GPIO) control of up to 132 input/output pins (package dependent) All GPIO pins can be independently configured to support pull-up, pull down, or no pull Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 13
* * * *
All peripheral pins can be alternatively configured as both general purpose input or output pins except ADC channels which support alternative configuration as general purpose inputs Direct readback of the pin value supported on all digital output pins through the SIU Configurable digital input filter that can be applied to up to 14 general purpose input pins for noise elimination on external interrupts Register configuration protected against change with soft lock for temporary guard or hard lock to prevent modification until next reset.
1.6.9
*
Flash memory
Up to 1 MB of burst flash memory -- Typical flash memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss at 64 MHz -- Two 4128-bit page buffers with programmable prefetch control - 1 set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any access - 1 set of page buffers allocated to Display Controller Unit and the eDMA -- 64-bit ECC with single-bit correction, double-bit detection for data integrity -- 64 KB data flash memory -- separate 416 KB flash block for EEPROM emulation with prefetch buffer and 128-bit data access port Small block flash memory arrangement to support features such as boot block, operating system block Hardware managed flash memory writes, erase and verify sequence Censorship protection scheme to prevent flash memory content visibility Separate dedicated 64 KB data flash memory for EEPROM emulation -- 4 erase sectors each containing 16 KB of memory -- Offers Read-While-Write functionality from main program space -- Same data retention and program erase specification as main program flash memory array
The MPC5606S microcontroller has the following flash memory features:
* * * *
1.6.10
* * * * *
SRAM
The MPC5606S microcontrollers have up to 48 KB general-purpose on-chip SRAM with the following features: Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block 32-bit ECC with single-bit correction, double bit detection for data integrity Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory User transparent ECC encoding and decoding for byte, half word, and word accesses Separate internal power domain applied to full SRAM block, 8 KB SRAM block during STANDBY modes to retain contents during low power mode.
1.6.11
* * *
On-chip graphics SRAM
The MPC5606S microcontroller has 160 KB on-chip graphics SRAM with the following features: Usable as general purpose SRAM Typical SRAM access time: 0 wait-state for reads and 32-bit writes Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
MPC5606S Microcontroller Data Sheet, Rev. 6 14 Freescale Semiconductor
1.6.12
* * * * * * *
Memory Protection Unit (MPU)
The MPU features the following: 12 region descriptors for per master protection Start and end address defined with 32-byte granularity Overlapping regions supported Protection attributes can optionally include process ID Protection offered for 3 concurrent read ports Read and write attributes for all masters Execute and supervisor/user mode attributes for processor masters
1.6.13
Boot Assist Module (BAM)
The BAM is a block of read-only memory that is programmed once by Freescale. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are: * * * * * * * Booting from internal flash memory Serial boot loading (A program is downloaded into RAM via FlexCAN or LINFlex and then executed) Booting from external memory Enables and manages the transition of the MCU from reset to user code execution Configures device for serial bootload Enables multiple bootcode starting locations out of reset through implementation of search for valid Reset Configuration Halfword Enables or disables software watchdog timer out of reset through BAM read of Reset Configuration Halfword option bit
Additionally the BAM:
1.6.14
Enhanced Modular Input/Output System (eMIOS)
MPC5606S microcontrollers have two eMIOS modules--one with 16 channels and one with 8--with input/output channels supporting a range of 16-bit input capture, output compare, and Pulse Width Modulation functions. The modules are configurable and can implement 8-channel, 16-bit input capture/output compare or 16-channel, 16-bit output pulse width modulation/input compare/output compare. Up to five additional channels are configurable as modulus counters. eMIOS other features include: * * * * * Selectable clock source from main FMPLL, auxiliary FMPLL, external 4-16 MHz oscillator or 16 MHz Internal RC oscillator Timed I/O channels with 16-bit counter resolution Buffered updates Support for shifted PWM outputs to minimize occurrence of concurrent edges Edge aligned output pulse width modulation -- Programmable pulse period and duty cycle -- Supports 0% and 100% duty cycle -- Shared or independent time bases Programmable phase shift between channels Selectable combination of pairs of eMIOS outputs to support sound generation DMA transfer support
* * *
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 15
*
Selectable clock source from the primary FMPLL, auxiliary FMPLL, external 4-16 MHz oscillator or the 16 MHz internal RC oscillator. Table 3. 16-Channel eMIOS module channel configuration
Channel number
Channel mode
The channel configuration options for the 16-channel eMIOS module are summarized in Table 3.
8 IC/OC Counter
9-15 IC/OC X X X
16 PWM Counter X X X X X X
17-22 PWM X X X
23 PWM Counter X X X X
General Purpose Input/Output Single Action Input Capture Single Action Output Compare Modulus Counter Buffered1 Output Pulse Width and Frequency Modulation Buffered Output Pulse Width Modulation Buffered
1
X X X X
X X
X X
Modulus up and down counters to support driving local and global counter busses
The channel configuration options for the 8-channel eMIOS module are summarized in Table 4. Table 4. 8-Channel eMIOS module channel configuration
Channel number Channel mode 16 PWM Counter General Purpose Input/Output Single Action Input Capture Single Action Output Compare Modulus Counter Buffered1 Output Pulse Width and Frequency Modulation Buffered Output Pulse Width Modulation Buffered
1
17-22 PWM X X X
23 PWM Counter X X X X
X X X X X X
X X
X X
Modulus up and down counters to support driving local and global counter busses
1.6.15
* * * *
Analog-to-Digital Converter (ADC)
The ADC features the following: 10-bit A/D resolution 0 to 5 V common mode conversion range Supports conversions speeds of up to 1 s 16 internal and 8 external channels support
MPC5606S Microcontroller Data Sheet, Rev. 6 16 Freescale Semiconductor
*
*
* * * * * * *
* * *
Up to 16 single-ended inputs channels -- All channels configured to have alternate function as general purpose input/output pins - 10-bit 3 counts accuracy (TUE) External multiplexer support to increase up to 23 channels -- Automatic 1 x 8 multiplexer control -- External multiplexer connected to a dedicated input channel -- Shared register between the 8 external channels Result register available for every non-multiplexed channel Configurable Left or Right aligned result format Supports for one-shot, scan and injection conversion modes Injection mode status bit implemented on adjacent 16-bit register for each result -- Supports Access to Result and injection status with single 32-bit read Independently enabling of function for channels: -- Offset Refresh Conversion Triggering support -- Internal conversion triggering from periodic interrupt timer (PIT) 4 configurable analog comparator channels offering range comparison with triggered alarm -- Greater than -- Less than -- Out of range All unused analog inputs can be used as general purpose input and output pins Power Down mode Optional support for DMA transfer of results
1.6.16
Deserial Serial Peripheral Interface (DSPI)
The deserial serial peripheral interface (DSPI) modules provide a synchronous serial interface for communication between the MPC5606S MCU and external devices. The DSPI features the following: * * * * * * * * * * * * * * Up to two DSPI modules Full duplex, synchronous transfers Master or slave operation Programmable master bit rates Programmable clock polarity and phase End-of-transmission interrupt flag Programmable transfer baud rate Programmable data frames from 4 to 16 bits Up to 6 chip select lines available, depending on package and pin multiplexing, enable 64 external devices to be selected using external muxing from a single DSPI 8 clock and transfer attributes registers Chip select strobe available as alternate function on one of the chip select pins for deglitching FIFOs for buffering up to 4 transfers on the transmit and receive side General purpose I/O functionality on pins when not used for SPI Queueing operation possible through use of eDMA
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 17
1.6.17
FlexCAN
The MPC5606S MCU contains two controller area network (FlexCAN) modules. The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCan modules offer the following: * * * Compliant with CAN protocol specification, Version 2.0B active 64 mailboxes, each configurable as transmit or receive -- Mailboxes configurable while module remains synchronized to CAN bus Transmit features -- Supports configuration of multiple mailboxes to form message queues of scalable depth -- Arbitration scheme according to message ID or message buffer number -- Internal arbitration to guarantee no inner or outer priority inversion -- Transmit abort procedure and notification Receive features -- Individual programmable filters for each mailbox -- 8 mailboxes configurable as a 6-entry receive FIFO -- 8 programmable acceptance filters for receive FIFO Programmable clock source -- System clock -- Direct oscillator clock to avoid PLL jitter Listen only mode capabilities CAN Sampler -- Can catch the 1st message sent on the CAN network while the MPC5606S is stopped. This guarantees a clean startup of the system without missing messages on the CAN network. -- The CAN sampler is connected to one of the CAN RX pins.
*
*
* *
1.6.18
Serial communication interface module (LINFlex)
The MPC5606S devices include up to two LINFlex modules and support for LIN Master mode, LIN Slave mode and UART mode. The modules are LIN state machine compliant to the LIN 1.3 and 2.0 and 2.1 Specifications and handle LIN frame transmission and reception without CPU intervention. Other features include: * * * * * * * * * Autonomous LIN frame handling Message buffer to store identifier and up to eight data bytes Supports message length of up to 64 bytes Detection and flagging of LIN errors Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors Classic or extended checksum calculation Configurable Break duration of up to 36-bit times Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional) Diagnostic features -- Loop back -- Self Test -- LIN bus stuck dominant detection
MPC5606S Microcontroller Data Sheet, Rev. 6 18 Freescale Semiconductor
* *
*
Interrupt driven operation with 16 interrupt sources LIN slave mode features -- Autonomous LIN header handling -- Autonomous LIN response handling -- Discarding of irrelevant LIN responses using up to 16 ID filters UART mode -- Full-duplex operation -- Standard non return-to-zero (NRZ) mark/space format -- Data buffers with 4-byte receive, 4-byte transmit -- Configurable word length (8-bit or 9-bit words) -- Error detection and flagging - Parity, noise and framing errors -- Interrupt driven operation with 4 interrupts sources -- Separate transmitter and receiver CPU interrupt sources -- 16-bit programmable baud-rate modulus counter and 16-bit fractional -- 2 receiver wake-up methods
1.6.19
System clocks and clock generation modules
The system clock on the MPC5606S can be derived from an external oscillator, an on-chip FMPLL, or the internal 16 MHz oscillator. * * * The source system clock frequency can be changed via an on-chip programmable clock divider (1 to 2). Additional programmable peripheral bus clock divider ratio (1 to 16) The MPC5606S has 2 on-chip FMPLLs--the primary module and an auxiliary module. -- Each features the following: - Input clock frequency from 4 MHz to 16 MHz - Lock detect circuitry continuously monitors lock status - Loss Of Clock (LOC) detection for reference and feedback clocks - On-chip loop filter (for improved electromagnetic interference performance and reduction of number of external components required) - Support for frequency ramping from PLL -- The primary FMPLL module is for use as a system clock source. The auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation. The main oscillator provides the following features: -- Input frequency range 4-16 MHz -- Square-wave input mode -- Oscillator input mode 3.3 V (5.0 V) -- Automatic level control -- PLL reference MPC5606S includes a 32 KHz low power external oscillator for slow execution, low power, and Real Time Clock Dedicated internal 128 kHz RC oscillator for low power mode operation and self wake-up -- 10% accuracy across voltage and temperature (after factory trimming) -- Trimming registers to support improved accuracy with in-application calibration Dedicated 16 MHz internal RC oscillator -- Used as default clock source out of reset
*
* *
*
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 19
-- -- -- -- --
Provides a clock for rapid start-up from low power modes Provides a back-up clock in the event of PLL or External Oscillator clock failure Offers an independent clock source for the Watchdog timer 5% accuracy across voltage and temperature (after factory trimming) Trimming registers to support frequency adjustment with in-application calibration
1.6.20
* * * * *
Periodic Interrupt Timer module (PIT)
The PIT features the following: 4 general purpose interrupt timers Up to 2 dedicated interrupt timers for triggering ADC conversions 32-bit counter resolution Clocked by system clock frequency 32-bit counter for Real Time Interrupt, clocked from main external oscillator
1.6.21
*
Real Time Counter (RTC)
Real Timer Counter supports wake-up from Low Power modes or Real Time Clock generation Configurable resolution for different timeout periods -- 1 s resolution for >1 hour period -- 1 ms resolution for 2 second period Selectable clock sources from external 32 KHz crystal, external 4-16 MHz crystal, internal 128 kHz RC oscillator or divided internal 16 MHz RC oscillator
*
1.6.22
System Timer Module (STM)
The STM is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). * * * * One 32-bit up counter with 8-bit prescaler Four 32-bit compare channels Independent interrupt source for each channel Counter can be stopped in debug mode
1.6.23
* * * * * *
Software Watchdog Timer (SWT)
The Watchdog features the following: Watchdog supporting software activation or enabled out of Reset Supports normal or windowed mode Watchdog timer value writable once after reset Watchdog supports optional halting during low power modes Configurable response on timeout: reset, interrupt, or interrupt followed by reset Selectable clock source for main system clock or internal 16 MHz RC oscillator clock
MPC5606S Microcontroller Data Sheet, Rev. 6 20 Freescale Semiconductor
1.6.24
Display Control Unit (DCU)
The DCU is a display controller designed to drive TFT LCD displays capable of driving up to WQVGA resolution screens with 16 layers and 4 planes with real time alpha-blending. The DCU generates all the necessary signals required to drive the display: up to 24-bit RGB data bus, Pixel Clock, Data Enable, Horizontal-Sync and Vertical-Sync. Internal memory resource of the MPC5606S allows to easily handle complex graphics contents (pictures, icons, languages, fonts) on a color TFT panel in up to Wide Quarter Video Graphics Array (WQVGA) sizes. All the data fetches from internal and/or external memory are performed by the internal four-channel DMA of the DCU providing a high speed/low latency access to the system backbone. Control Descriptors (CDs) associated with each layer enable effective merging of different resolutions into one plane to optimize use of internal memory buffers. A layer may be constructed from graphic content of various resolutions including 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, 24bpp and 24bpp+alpha. The ability of the DCU to handle input data in resolutions as low as 1bpp, 2bpp and 4bpp enables a highly efficient use of internal memory resources of the MPC5606S. A special tiled mode can be enabled on any of the 16 layers to repeat a pattern optimizing graphic memory usage. A hardware cursor can be managed independently of the layers at blending level increasing the efficient use of the internal DCU resources. To secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical data along the whole system data path from the memory to the TFT pads. The DCU features the following: * * * * * * * * * * * * Display color depth: up to 24 bpp Generation of all RGB and control signals for TFT Four-plane blending Maximum number of Input Layers: 16 (fixed priority) Dynamic Look-Up-Table (Color and Gamma Look-Up) blending range: up to 256 levels Transparency Mode Gamma Correction Tiled mode on all the layers Hardware Cursor Critical display content integrity monitoring for Functional Safety support Internal Direct Memory Access (DMA) module to transfer data from internal and / or external memory.
1.6.25
Parallel Data Interface (PDI)
The PDI is a digital interface used to receive external digital video or graphic content into the DCU. The PDI input is directly injected into the DCU background plane FIFO. When the PDI is activated, all the DCU synchronization is extracted from the external video stream to guarantee the synchronization of the two video sources. The PDI can be used to: * * * * * Connect a Video Camera output directly to the PDI Connect a secondary display driver as slave with a minimum of extra cost Connect a device gathering various Video sources Provide flexibility to allow the DCU to be used in slave mode (external synchronization) Supported color modes:
The PDI features the following:
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 21
*
* *
-- 8-bit mono -- 8-bit color multiplexed -- RGB565 -- 16-bit/18-bit RAW color Supported synchronization modes: -- Embedded ITU-R BT.656-4 (RGB565 mode 2) -- HSYNC, VSYNC -- Data Enable Direct interface with DCU background plane FIFO Synchronization generation for the DCU
1.6.26
* *
Liquid Crystal Display (LCD) driver
The LCD driver module has two configurations allowing a maximum of 160 or 228 LCD segments: Up to 40 frontplane drivers and 4 backplane drivers Up to 38 frontplane drivers and 6 backplane drivers
Each segment is controlled and can be masked by a corresponding bit in the LCD RAM. Four to six multiplex modes (1/1, 1/2, 1/3, 1/4, 1/5, 1/6 duty), and three bias (1/1, 1/2, 1/3) methods are available. All frontplane and backplane pins can be multiplexed with other port functions. The LCD driver module features the following: * Programmable frame clock generator from different clock sources: -- System clock -- Internal RC oscillator Programmable bias voltage level selector On-chip generation of all output voltage levels -- LCD voltage reference taken from main 5V supply LCD RAM - contains the data to be displayed on the LCD -- Data can be read from or written to the display RAM at any time End of Frame interrupt: -- To optimize the refresh of the data without visual artefact -- Selectable number of frames between each interrupt Contrast adjustment using programmable internal voltage reference Remapping capability of 4 or 6 backplanes with frontplanes; -- To increase pin selection flexibility In low power modes, the LCD operation can be suspended under software control. The LCD can also operate in low power modes, clocked by the internal 128 kHz IRC or external 32 KHz crystal oscillator Selectable output current boost during transitions
* * * *
* * * *
1.6.27
Stepper Motor Controller (SMC)
The SMC module is a PWM motor controller suitable to drive instruments in a cluster configuration or any other loads requiring a PWM signal. The motor controller has twelve PWM channels associated with two pins each (24 pins in total). The SMC module includes the following features: * * 10/11-bit PWM counter 11-bit resolution with selectable PWM dithering function
MPC5606S Microcontroller Data Sheet, Rev. 6 22 Freescale Semiconductor
* * *
Left, right, or center aligned PWM Output slew rate control Output Short Circuit Detection
This module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. This module can be used for other motor control or PWM applications that match the frequency, resolution, and output drive capabilities of the module.
1.6.28
Stepper Stall Detect (SSD)
The stepper stall detector (SSD) module provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (RTZ). The SSD module features the following: * * * * * Programmable full step state Programmable integration polarity Blanking (recirculation) state 16-bit integration accumulator register 16-bit modulus down counter with interrupt
1.6.29
*
Sound Generation Logic (SGL)
The SGL has two modes of operation: Amplitude modulated PWM mode for low cost buzzers using any two eMIOS channels: -- Monophonic signal with amplitude control -- 8-bit amplitude resolution -- Ability to mix any two eMIOS channels. -- Requires simple external RC lowpass filter Digital sample mode for higher quality sound using one eMIOS channel and eDMA -- Up to 10-bit audio amplitude resolution -- Polyphonic sound synthesis -- Playback of sample based waveforms -- Text-to-speech possibility -- Requires external lowpass filter
*
1.6.30
* *
IEEE 1149.1 JTAG Controller (JTAGC)
JTAGC features the following: Backward compatible to standard JTAG IEEE 1149.1-2001 test access port (TAP) interface Support for boundary scan testing
1.6.31
* *
Nexus Development Interface (NDI)
Nexus features the following: Per IEEE-ISTO 5001-2003 Nexus 2 Plus features supported -- Static debug -- Watchpoint messaging
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 23
* *
Ownership trace messaging Program trace messaging Real time read/write of any internally memory mapped resources through JTAG pins Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow overwrite of information -- Watchpoint triggering, watchpoint triggers program tracing Configured via the IEEE 1149.1 (JTAG) port Nexus Auxiliary port supported on the 176 LQFP and 208-pin BGA package FOR DEVELOPMENT ONLY -- Narrow Auxiliary Nexus port supporting support trace, with 2 MDO pins -- Wide Auxiliary Nexus port supporting higher bandwidth trace, with 4 MDO pins
-- -- -- --
2
2.1
Pinout and signal descriptions
144 LQFP package pinouts
CAUTION
Any pins labeled "NC" must not be connected to any external circuit.
This section shows the pinouts for the 144-pin LQFP packages.
MPC5606S Microcontroller Data Sheet, Rev. 6 24 Freescale Semiconductor
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 (see detail inset) PA10 (see detail inset) PA11 (see detail inset) PA12 (see detail inset) PA13 (see detail inset) PA14 (see detail inset) PA15 VDDE_A VSSE_A (see detail inset) PG0 FP6/SDA_3/DCU_B1/GPIO[87]/PG1 (see detail inset) PG2 (see detail inset) PG3 (see detail inset) PG4 FP2/eMIOSA8/DCU_B5/GPIO[91]/PG5 FP1/DCU_B6/GPIO[92]/PG6 FP0/DCU_B7/GPIO[93]/PG7 BP0/DCU_VSYNC/GPIO[94]/PG8 BP1/DCU_HSYNC/GPIO[95]/PG9 BP2/DCU_DE/GPIO[96]/PG10 BP3/DCU_PCLK/GPIO[97]/PG11 VLCD/GPIO[104]/PH5 VDDR VSSR RESET VRC_CTRL VPP XTAL VSSOSC EXTAL VSSPLL VDDPLL VREG_BYPASS TDI/GPIO[100]/PH1 TDO/GPIO[101]/PH2 TMS/GPIO[102]/PH3 TCK/GPIO[99]/PH0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PA9/GPIO[9]/DCU_G1/eMIOSB18/SDA_2/FP14 PA8/GPIO[8]/DCU_G0/eMIOSB23/SCL_2/FP15 PA7/GPIO[7]/DCU_R7/eMIOSA16/FP16 PA6/GPIO[6]/DCU_R6/eMIOSA15/FP17 PA5/GPIO[5]/DCU_R5/eMIOSA17/FP18 PA4/GPIO[4]/DCU_R4/eMIOSA18/FP19 PA3/GPIO[3]/DCU_R3/eMIOSA19/FP20 PA2/GPIO[2]/DCU_R2/eMIOSA20/FP21 PA1/GPIO[1]/DCU_R1/eMIOSA21/FP22 PA0/GPIO[0]/DCU_R0/eMIOSA22/SOUND/FP23 VSS12 VDD12 PF15/GPIO[85]/SCK_2/FP24 PF14/GPIO[84]/SOUT_2/CANTX_1/FP25 PF13/GPIO[83]/SIN_2/CANRX_1/FP26 PF12/GPIO[82]/eMIOSB16/PCS2_2/FP27 PF11/GPIO[81]/eMIOSB23/PCS1_2/FP28 PF10/GPIO[80]/eMIOSA16/PCS0_2/FP29 PG12/GPIO[98]/eMIOSA23/SOUND/eMIOSA8/FP30 VSSE_A VDDE_A PF9/GPIO[79]/SCL_1/PCS0_1/TXD_1/FP31 PF8/GPIO[78]/SDA_1/PCS1_1/RXD_1/FP32 PF7/GPIO[77]/SCL_0/PCS2_1/FP33 PF6/GPIO[76]/SDA_0/FP34 VSS12 VDD12 PF5/GPIO[75]/eMIOSA9/DCU_TAG/FP35 PF4/GPIO[74]/eMIOSA10/PDI7/FP36 PF3/GPIO[73]/eMIOSA11/PDI6/FP37 PF1/GPIO[71]/eMIOSA12/PDI5/eMIOSA21/FP38 PF0/GPIO[70]/eMIOSA13/PDI4/eMIOSA22/FP39 PB2/GPIO[18]/TXD_0 PB3/GPIO[19]/RXD_0 VSSE_E VDDE_E
144-Pin LQFP
Detail:
FP13/eMIOSB20/DCU_G2/GPIO[10]/PA10 - FP12/eMIOSA13/DCU_G3/GPIO[11]/PA11 - FP11/eMIOSA12/DCU_G4/GPIO[12]/PA12 - FP10/eMIOSA11/DCU_G5/GPIO[13]/PA13 - FP9/eMIOSA10/DCU_G6/GPIO[14]/PA14 - FP8/eMIOSA9/DCU_G7/GPIO[15]/PA15 - FP7/SOUND/SCL_3/DCU_B0/GPIO[86]/PG0 - FP5/eMIOSB19/DCU_B2/GPIO[88]/PG2 - FP4/eMIOSB21/DCU_B3/GPIO[89]/PG3 - FP3/eMIOSB17/DCU_B4/GPIO[90]/PG4 -
PB11/GPIO[27]/CANTX_1/PDI3/eMIOSA16 PB10GPIO[26]//CANRX_1/PDI2/eMIOSA23 PB0/GPIO[16]/CANTX_0/PDI1 PB1/GPIO[17]/CANRX_0/PDI0 VSS12 VDD12 PE7/GPIO[69]/M5C1P/SSD5_3/eMIOSA8 PE6/GPIO[68]/M5C1M/SSD5_2/eMIOSA9 PE5/GPIO[67]/M5C0P/SSD5_1/eMIOSA10 PE4/GPIO[66]/M5C0M/SSD5_0/eMIOSA11 VSSMC VDDMC PE3/GPIO[65]/M4C1P/SSD4_3/eMIOSA12 PE2/GPIO[64]/M4C1M/SSD4_2/eMIOSA13 PE1/GPIO[63]/M4C0P/SSD4_1/eMIOSA14 PE0/GPIO[62]/M4C0M/SSD4_0/eMIOSA15 PD15/GPIO[61]/M3C1P/SSD3_3 PD14/GPIO[60]/M3C1M/SSD3_2 PD13/GPIO[59]/M3C0P/SSD3_1 PD12/GPIO[58/M3C0M/SSD3_0 VSSMB VDDMB PD11/GPIO[57]/M2C1P/SSD2_3 PD10/GPIO[56]/M2C1M/SSD2_2 PD9/GPIO[55]/M2C0P/SSD2_1 PD8/GPIO[54]/M2C0M/SSD2_0 PD7/GPIO[53]/M1C1P/SSD1_3/eMIOSB16 PD6/GPIO[52]/M1C1M/SSD1_2/eMIOSB17 PD5/GPIO[51]/M1C0P/SSD1_1/eMIOSB18 PD4/GPIO[50]/M1C0M/SSD1_0/eMIOSB19 VSSMA VDDMA PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20 PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21 PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22 PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23
Freescale Semiconductor
NMI/GPIO[72]/PF2 VDDE_B VSSE_B PCS2_0/eMIOSB19/RXD_1/GPIO[28]/PB12 PCS1_0/eMIOSB18/TXD_1/GPIO[29]/PB13 VDD12 VSS12 eMIOSB20/SCK_0/GPIO[25]/PB9 eMIOSB21/SOUT_0/GPIO[24]/PB8 eMIOSB22/SIN_0/GPIO[23]/PB7 CLKOUT/eMIOSB16/PCS0_0/GPIO[103]/PH4 MA0/SCK_1/GPIO[20]/PB4 FABM/MA1/SOUT_1/GPIO[21]/PB5 ABS[0]/MA2/SIN_1/GPIO[22]/PB6 VDD12 VSS12 VDDA VSSA XTAL32/ANS15/GPIO[45]/PC15 EXTAL32/ANS14/GPIO[44]/PC14 PCS0_1/MA2/ANS13/GPIO[43]/PC13 PCS1_1/MA1/ANS12/GPIO[42]/PC12 PCS2_1/MA0/ANS11/GPIO[41]/PC11 SOUND/ANS10(mux)/GPIO[40]/PC10 ANS9/GPIO[39]/PC9 ANS8/GPIO[38]/PC8 VDDE_C VSSE_C ANS7/GPIO[37]/PC7 ANS6/GPIO[36]/PC6 ANS5/GPIO[35]/PC5 ANS4/GPIO[34]/PC4 ANS3/GPIO[33]/PC3 ANS2/GPIO[32]/PC2 ANS1/GPIO[31]/PC1 ANS0/GPIO[30]/PC0
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 2. 144-pin LQFP pinout for MPC5606S
MPC5606S Microcontroller Data Sheet, Rev. 6 25
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 (see detail inset) PA10 (see detail inset) PA11 (see detail inset) PA12 (see detail inset) PA13 (see detail inset) PA14 (see detail inset) PA15 VDDE_A VSSE_A (see detail inset) PG0 FP6/GPIO[87]/PG1 (see detail inset) PG2 (see detail inset) PG3 (see detail inset) PG4 FP2/eMIOSA8/GPIO[91]/PG5 FP1/GPIO[92]/PG6 FP0/GPIO[93]/PG7 BP0/GPIO[94]/PG8 BP1/GPIO[95]/PG9 BP2/GPIO[96]/PG10 BP3/GPIO[97]/PG11 VLCD/GPIO[104]/PH5 VDDR VSSR RESET VRC_CTRL VPP XTAL VSSOSC EXTAL VSSPLL VDDPLL VREG_BYPASS TDI/GPIO[100]/PH1 TDO/GPIO[101]/PH2 TMS/GPIO[102]/PH3 TCK/GPIO[99]/PH0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PA9/GPIO[9]/eMIOSB18/FP14 PA8/GPIO[8]/eMIOSB23/FP15 PA7/GPIO[7]/eMIOSA16/FP16 PA6/GPIO[6]/eMIOSA15/FP17 PA5/GPIO[5]/eMIOSA17/FP18 PA4/GPIO[4]/eMIOSA18/FP19 PA3/GPIO[3]/eMIOSA19/FP20 PA2/GPIO[2]/eMIOSA20/FP21 PA1/GPIO[1]/eMIOSA21/FP22 PA0/GPIO[0]/eMIOSA22/SOUND/FP23 VSS12 VDD12 PF15/GPIO[85]/FP24 PF14/GPIO[84]/CANTX_1/FP25 PF13/GPIO[83]/CANRX_1/FP26 PF12/GPIO[82]/eMIOSB16/FP27 PF11/GPIO[81]/eMIOSB23/FP28 PF10/GPIO[80]/eMIOSA16/FP29 PG12/GPIO[98]/eMIOSA23/SOUND/eMIOSA8/FP30 VSSE_A VDDE_A PF9/GPIO[79]/SCL_1/PCS1_0/TXD_1/FP31 PF8/GPIO[78]/SDA_1/PCS1_1/RXD_1/FP32 PF7/GPIO[77]/SCL_0/PCS2_1/FP33 PF6/GPIO[76]/SDA_0/FP34 VSS12 VDD12 PF5/GPIO[75]/eMIOSA9/FP35 PF4/GPIO[74]/eMIOSA10/FP36 PF3/GPIO[73]/eMIOSA11/FP37 PF1/GPIO[71]/eMIOSA12/eMIOSA21/FP38 PF0/GPIO[70]/eMIOSA13/eMIOSA22/FP39 PB2/GPIO[18]/TXD_0 PB3/GPIO[19]/RXD_0 VSSE_E VDDE_E
144-pin LQFP MPC5604S
Detail:
FP13/eMIOSB20/GPIO[10]/PA10 - FP12/eMIOSA13/GPIO[11]/PA11 - FP11/eMIOSA12/GPIO[12]/PA12 - FP10/eMIOSA11/GPIO[13]/PA13 - FP9/eMIOSA10/GPIO[14]/PA14 - FP8/eMIOSA9/GPIO[15]/PA15 - FP7/SOUND/GPIO[86]/PG0 - FP5/eMIOSB19/GPIO[88]/PG2 - FP4/eMIOSB21/GPIO[89]/PG3 - FP3/eMIOSB17/GPIO[90]/PG4 -
PB11/GPIO[27]/CANTX_1/eMIOSA16 PB10GPIO[26]//CANRX_1/eMIOSA23 PB0/GPIO[16]/CANTX_0 PB1/GPIO[17]/CANRX_0 VSS12 VDD12 PE7/GPIO[69]/M5C1P/SSD5_3/eMIOSA8 PE6/GPIO[68]/M5C1M/SSD5_2/eMIOSA9 PE5/GPIO[67]/M5C0P/SSD5_1/eMIOSA10 PE4/GPIO[66]/M5C0M/SSD5_0/eMIOSA11 VSSMC VDDMC PE3/GPIO[65]/M4C1P/SSD4_3/eMIOSA12 PE2/GPIO[64]/M4C1M/SSD4_2/eMIOSA13 PE1/GPIO[63]/M4C0P/SSD4_1/eMIOSA14 PE0/GPIO[62]/M4C0M/SSD4_0/eMIOSA15 PD15/GPIO[61]/M3C1P/SSD3_3 PD14/GPIO[60]/M3C1M/SSD3_2 PD13/GPIO[59]/M3C0P/SSD3_1 PD12/GPIO[58/M3C0M/SSD3_0 VSSMB VDDMB PD11/GPIO[57]/M2C1P/SSD2_3 PD10/GPIO[56]/M2C1M/SSD2_2 PD9/GPIO[55]/M2C0P/SSD2_1 PD8/GPIO[54]/M2C0M/SSD2_0 PD7/GPIO[53]/M1C1P/SSD1_3/eMIOSB16 PD6/GPIO[52]/M1C1M/SSD1_2/eMIOSB17 PD5/GPIO[51]/M1C0P/SSD1_1/eMIOSB18 PD4/GPIO[50]/M1C0M/SSD1_0/eMIOSB19 VSSMA VDDMA PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20 PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21 PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22 PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23
26
NMI/GPIO[72]/PF2 VDDE_B VSSE_B PCS2_0/eMIOSB19/RXD_1/GPIO[28]/PB12 PCS1_0/eMIOSB18/TXD_1/GPIO[29]/PB13 VDD12 VSS12 eMIOSB20/SCK_0/GPIO[25]/PB9 eMIOSB21/SOUT_0/GPIO[24]/PB8 eMIOSB22/SIN_0/GPIO[23]/PB7 CLKOUT/eMIOSB16/PCS0_0/GPIO[103]/PH4 MA0/SCK_1/GPIO[20]/PB4 FABM/MA1/SOUT_1/GPIO[21]/PB5 ABS[0]/MA2/SIN_1/GPIO[22]/PB6 VDD12 VSS12 VDDA VSSA XTAL32/ANS15/GPIO[45]/PC15 EXTAL32/ANS14/GPIO[44]/PC14 PCS0_1/MA2/ANS13/GPIO[43]/PC13 PCS1_1/MA1/ANS12/GPIO[42]/PC12 PCS2_1/MA0/ANS11/GPIO[41]/PC11 SOUND/ANS10(mux)/GPIO[40]/PC10 ANS9/GPIO[39]/PC9 ANS8/GPIO[38]/PC8 VDDE_C VSSE_C ANS7/GPIO[37]/PC7 ANS6/GPIO[36]/PC6 ANS5/GPIO[35]/PC5 ANS4/GPIO[34]/PC4 ANS3/GPIO[33]/PC3 ANS2/GPIO[32]/PC2 ANS1/GPIO[31]/PC1 ANS0/GPIO[30]/PC0
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 3. 144-pin LQFP pinout for MPC5604S
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 (see detail inset) PA10 (see detail inset) PA11 (see detail inset) PA12 (see detail inset) PA13 (see detail inset) PA14 (see detail inset) PA15 VDDE_A VSSE_A (see detail inset) PG0 FP6/GPIO[87]/PG1 (see detail inset) PG2 (see detail inset) PG3 (see detail inset) PG4 FP2/eMIOSA8/GPIO[91]/PG5 FP1/GPIO[92]/PG6 FP0/GPIO[93]/PG7 BP0/GPIO[94]/PG8 BP1/GPIO[95]/PG9 BP2/GPIO[96]/PG10 BP3/GPIO[97]/PG11 VLCD/GPIO[104]/PH5 VDDR VSSR RESET VRC_CTRL VPP XTAL VSSOSC EXTAL VSSPLL VDDPLL VREG_BYPASS TDI/GPIO[100]/PH1 TDO/GPIO[101]/PH2 TMS/GPIO[102]/PH3 TCK/GPIO[99]/PH0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PA9/GPIO[9]/eMIOSB18/FP14 PA8/GPIO[8]/eMIOSB23/FP15 PA7/GPIO[7]/eMIOSA16/FP16 PA6/GPIO[6]/eMIOSA15/FP17 PA5/GPIO[5]/eMIOSA17/FP18 PA4/GPIO[4]/eMIOSA18/FP19 PA3/GPIO[3]/eMIOSA19/FP20 PA2/GPIO[2]/eMIOSA20/FP21 PA1/GPIO[1]/eMIOSA21/FP22 PA0/GPIO[0]/eMIOSA22/SOUND/FP23 VSS12 VDD12 PF15/GPIO[85]/FP24 PF14/GPIO[84]/FP25 PF13/GPIO[83]/FP26 PF12/GPIO[82]/eMIOSB16/FP27 PF11/GPIO[81]/eMIOSB23/FP28 PF10/GPIO[80]/eMIOSA16/FP29 PG12/GPIO[98]/eMIOSA23/SOUND/eMIOSA8/FP30 VSSE_A VDDE_A PF9/GPIO[79]/SCL_1/PCS1_0/TXD_1/FP31 PF8/GPIO[78]/SDA_1/PCS1_1/RXD_1/FP32 PF7/GPIO[77]/SCL_0/PCS2_1/FP33 PF6/GPIO[76]/SDA_0/FP34 VSS12 VDD12 PF5/GPIO[75]/eMIOSA9/FP35 PF4/GPIO[74]/eMIOSA10/FP36 PF3/GPIO[73]/eMIOSA11/FP37 PF1/GPIO[71]/eMIOSA12/eMIOSA21/FP38 PF0/GPIO[70]/eMIOSA13/eMIOSA22/FP39 PB2/GPIO[18]/TXD_0 PB3/GPIO[19]/RXD_0 VSSE_E VDDE_E
144-pin LQFP MPC5602S
Detail:
FP13/eMIOSB20/GPIO[10]/PA10 - FP12/eMIOSA13/GPIO[11]/PA11 - FP11/eMIOSA12/GPIO[12]/PA12 - FP10/eMIOSA11/GPIO[13]/PA13 - FP9/eMIOSA10/GPIO[14]/PA14 - FP8/eMIOSA9/GPIO[15]/PA15 - FP7/SOUND/GPIO[86]/PG0 - FP5/eMIOSB19/GPIO[88]/PG2 - FP4/eMIOSB21/GPIO[89]/PG3 - FP3/eMIOSB17/GPIO[90]/PG4 -
PB11/GPIO[27]/eMIOSA16 PB10GPIO[26]/eMIOSA23 PB0/GPIO[16]/CANTX_0 PB1/GPIO[17]/CANRX_0 VSS12 VDD12 PE7/GPIO[69]/M5C1P/SSD5_3/eMIOSA8 PE6/GPIO[68]/M5C1M/SSD5_2/eMIOSA9 PE5/GPIO[67]/M5C0P/SSD5_1/eMIOSA10 PE4/GPIO[66]/M5C0M/SSD5_0/eMIOSA11 VSSMC VDDMC PE3/GPIO[65]/M4C1P/SSD4_3/eMIOSA12 PE2/GPIO[64]/M4C1M/SSD4_2/eMIOSA13 PE1/GPIO[63]/M4C0P/SSD4_1/eMIOSA14 PE0/GPIO[62]/M4C0M/SSD4_0/eMIOSA15 PD15/GPIO[61]/M3C1P/SSD3_3 PD14/GPIO[60]/M3C1M/SSD3_2 PD13/GPIO[59]/M3C0P/SSD3_1 PD12/GPIO[58/M3C0M/SSD3_0 VSSMB VDDMB PD11/GPIO[57]/M2C1P/SSD2_3 PD10/GPIO[56]/M2C1M/SSD2_2 PD9/GPIO[55]/M2C0P/SSD2_1 PD8/GPIO[54]/M2C0M/SSD2_0 PD7/GPIO[53]/M1C1P/SSD1_3/eMIOSB16 PD6/GPIO[52]/M1C1M/SSD1_2/eMIOSB17 PD5/GPIO[51]/M1C0P/SSD1_1/eMIOSB18 PD4/GPIO[50]/M1C0M/SSD1_0/eMIOSB19 VSSMA VDDMA PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20 PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21 PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22 PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23
Freescale Semiconductor
NMI/GPIO[72]/PF2 VDDE_B VSSE_B PCS2_0/eMIOSB19/RXD_1/GPIO[28]/PB12 PCS1_0/eMIOSB18/TXD_1/GPIO[29]/PB13 VDD12 VSS12 eMIOSB20/SCK_0/GPIO[25]/PB9 eMIOSB21/SOUT_0/GPIO[24]/PB8 eMIOSB22/SIN_0/GPIO[23]/PB7 CLKOUT/eMIOSB16/PCS0_0/GPIO[103]/PH4 MA0/SCK_1/GPIO[20]/PB4 FABM/MA1/SOUT_1/GPIO[21]/PB5 ABS[0]/MA2/SIN_1/GPIO[22]/PB6 VDD12 VSS12 VDDA VSSA XTAL32/ANS15/GPIO[45]/PC15 EXTAL32/ANS14/GPIO[44]/PC14 PCS0_1/MA2/ANS13/GPIO[43]/PC13 PCS1_1/MA1/ANS12/GPIO[42]/PC12 PCS2_1/MA0/ANS11/GPIO[41]/PC11 SOUND/ANS10(mux)/GPIO[40]/PC10 ANS9/GPIO[39]/PC9 ANS8/GPIO[38]/PC8 VDDE_C VSSE_C ANS7/GPIO[37]/PC7 ANS6/GPIO[36]/PC6 ANS5/GPIO[35]/PC5 ANS4/GPIO[34]/PC4 ANS3/GPIO[33]/PC3 ANS2/GPIO[32]/PC2 ANS1/GPIO[31]/PC1 ANS0/GPIO[30]/PC0
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 4. 144-pin LQFP pinout for MPC5602S
MPC5606S Microcontroller Data Sheet, Rev. 6 27
2.2
176 LQFP package pinout
CAUTION
Any pins labeled "NC" must not be connected to any external circuit.
PA9/GPIO[9]/DCU_G1/eMIOSB18/SDA_2/FP14 PA8/GPIO[8]/DCU_G0/eMIOSB23/SCL_2/FP15 PA7/GPIO[7]/DCU_R7/eMIOSA16/FP16 PA6/GPIO[6]/DCU_R6/eMIOSA15/FP17 PA5/GPIO[5]/DCU_R5/eMIOSA17/FP18 VSSE_A VDDE_A PA4/GPIO[4]/DCU_R4/eMIOSA18/FP19 PA3/GPIO[3]/DCU_R3/eMIOSA19/FP20 PA2/GPIO[2]/DCU_R2/eMIOSA20/FP21 PA1/GPIO[1]/DCU_R1/eMIOSA21/FP22 PA0/GPIO[0]/DCU_R0/eMIOSA22/SOUND/FP23 VSS12 VDD12 PF15/GPIO[85]/SCK_2/FP24 PF14/GPIO[84]/SOUT_2/CANTX_1/FP25 PF13/GPIO[83]/SIN_2/CANRX_1/FP26 PF12/GPIO[82]/eMIOSB16/PCS2_2/FP27 PF11/GPIO[81]/eMIOSB23/PCS1_2/FP28 PF10/GPIO[80]/eMIOSA16/PCS0_2/FP29 PG12/GPIO[98]/eMIOSA23/SOUND/eMIOSA8/FP30 VSSE_A VDDE_A PF9/GPIO[79]/SCL_1/PCS0_1/TXD_1/FP31 PF8/GPIO[78]/SDA_1/PCS1_1/RXD_1/FP32 PF7/GPIO[77]/SCL_0/PCS2_1/FP33 PF6/GPIO[76]/SDA_0/FP34 VSS12 VDD12 PF5/GPIO[75]/eMIOSA9/DCU_TAG/FP35 PF4/GPIO[74]/eMIOSA10/PDI7/FP36 PF3/GPIO[73]/eMIOSA11/PDI6/FP37 PF1/GPIO[71]/eMIOSA12/PDI5/eMIOSA21/FP38 PF0/GPIO[70]/eMIOSA13/PDI4/eMIOSA22/FP39 PK1/GPIO[122]/PDI13/eMIOSA17 PK0/GPIO[121]/PDI12/eMIOSA18/DCU_TAG PB2/GPIO[18]/TXD_0 PB3/GPIO[19]/RXD_0 PJ15/GPIO[120]/PDI11/eMIOSA19 PJ14/GPIO[119]/PDI10/eMIOSA20 PJ13/GPIO[118]/PDI9/eMIOSB20 PJ12/GPIO[117]/PDI8/eMIOSB17 VSSE_E VDDE_E (see detail inset) PA10 (see detail inset) PA11 (see detail inset) PA12 (see detail inset) PA13 (see detail inset) PA14 (see detail inset) PA15 VDDE_A VSSE_A (see detail inset) PG0 (see detail inset) PG1 (see detail inset) PG2 (see detail inset) PG3 (see detail inset) PG4 (see detail inset) PG5 FP1/DCU_B6/GPIO[92]/PG6 FP0/DCU_B7/GPIO[93]/PG7 (see detail inset) PG8 (see detail inset) PG9 BP2/DCU_DE/GPIO[96]/PG10 (see detail inset) PG11 VLCD/GPIO[104]/PH5 VDDR VSSR RESET VRC_CTRL VPP XTAL VSSOSC EXTAL VSSPLL VDDPLL VREG_BYPASS PDI10/MCKO/GPIO[123]/PK2 PDI11/MSEO/GPIO[124]/PK3 PDI12/EVTO/GPIO[125]/PK4 TDI/GPIO[100]/PH1 PDI13/EVTI/GPIO[126]/PK5 PDI14/MDO0/GPIO[127]/PK6 TDO/GPIO[101]/PH2 PDI15/MDO1/GPIO[128]/PK7 TMS/GPIO[102]/PH3 PDI16/MDO2/GPIO[129]/PK8 TCK/GPIO[99]/PH0 PDI17/MDO3/GPIO[130]/PK9 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
Figure 5 shows the pinout for the 176-pin LQFP package.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
176-Pin LQFP
Detail:
FP13/eMIOSB20/DCU_G2/GPIO[10]/PA10 - FP12/eMIOSA13/DCU_G3/GPIO[11]/PA11 - FP11/eMIOSA12/DCU_G4/GPIO[12]/PA12 - FP10/eMIOSA11/DCU_G5/GPIO[13]/PA13 - FP9/eMIOSA10/DCU_G6/GPIO[14]/PA14 - FP8/eMIOSA9/DCU_G7/GPIO[15]/PA15 - FP7/SOUND/SCL_3/DCU_B0/GPIO[86]/PG0 - FP6/SDA_3/DCU_B1/GPIO[87]/PG1 - FP5/eMIOSB19/DCU_B2/GPIO[88]/PG2 - FP4/eMIOSB21/DCU_B3/GPIO[89]/PG3 - FP3/eMIOSB17/DCU_B4/GPIO[90]/PG4 - FP2/eMIOSA8/DCU_B5/GPIO[91]/PG5 - BP0/DCU_VSYNC/GPIO[94]/PG8 - BP1/DCU_HSYNC/GPIO[95]/PG9 - BP3/DCU_PCLK/GPIO[97]/PG11 -
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
PB11/GPIO[27]/CANTX_1/PDI3/eMIOSA16 PB10/GPIO[26]/CANRX_1/PDI2/eMIOSA23 PB0/GPIO[16]/CANTX_0/PDI1 PB1/GPIO[17]/CANRX_0/PDI0 PJ11/GPIO[116]/PDI7 PJ10/GPIO[115]/PDI6 PJ9/GPIO[114]/PDI5 PJ8/GPIO[113]/PDI4 VSS12 VDD12 PJ3/GPIO[108]/PDI_PCLK PJ2/GPIO[107]/PDI_VSYNC PJ1/GPIO[106]/PDI_HSYNC PJ0/GPIO[105]/PDI_DE PE7/GPIO[69]/M5C1P/SSD5_3/eMIOSA8 PE6/GPIO[68]/M5C1M/SSD5_2/eMIOSA9 PE5/GPIO[67]/M5C0P/SSD5_1/eMIOSA10 PE4/GPIO[66]/M5C0M/SSD5_0/eMIOSA11 VSSMC VDDMC PE3/GPIO[65]/M4C1P/SSD4_3/eMIOSA12 PE2/GPIO[64]/M4C1M/SSD4_2/eMIOSA13 PE1/GPIO[63]/M4C0P/SSD4_1/eMIOSA14 PE0/GPIO[62]/M4C0M/SSD4_0/eMIOSA15 PD15/GPIO[61]/M3C1P/SSD3_3 PD14/GPIO[60]/M3C1M/SSD3_2 PD13/GPIO[59]/M3C0P/SSD3_1 PD12/GPIO[58]/M3C0M/SSD3_0 VSSMB VDDMB PD11/GPIO[57]/M2C1P/SSD2_3 PD10/GPIO[56]/M2C1M/SSD2_2 PD9/GPIO[55]/M2C0P/SSD2_1 PD8/GPIO[54]/M2C0M/SSD2_0 PD7/GPIO[53]/M1C1P/SSD1_3/eMIOSB16 PD6/GPIO[52]/M1C1M/SSD1_2/eMIOSB17 PD5/GPIO[51]/M1C0P/SSD1_1/eMIOSB18 PD4/GPIO[50]/M1C0M/SSD1_0/eMIOSB19 VSSMA VDDMA PD3/GPIO[49]/M0C1P/SSD0_3/eMIOSB20 PD2/GPIO[48]/M0C1M/SSD0_2/eMIOSB21 PD1/GPIO[47]/M0C0P/SSD0_1/eMIOSB22 PD0/GPIO[46]/M0C0M/SSD0_0/eMIOSB23
28
NMI/GPIO[72]/PF2 VDDE_B VSSE_B PCS2_0/eMIOSB19/RXD_1/GPIO[28]/PB12 PCS1_0/eMIOSB18/TXD_1/GPIO[29]/PB13 VDD12 VSS12 eMIOSA15/SDA_1/GPIO[131]/PK10 eMIOSA14/SCL_1/GPIO[132]/PK11 eMIOSB20/SCK_0/GPIO[25]/PB9 eMIOSB21/SOUT_0/GPIO[24]/PB8 eMIOSB22/SIN_0/GPIO[23]/PB7 CANRX_0/PDI0/GPIO[109]/PJ4 CANTX_0/PDI1/GPIO[110]/PJ5 eMIOSA22/CANRX_1/PDI2/GPIO[111]/PJ6 eMIOSA21/CANTX_1/PDI3/GPIO[112]/PJ7 CLKOUT/eMIOSB16/PCS0_0/GPIO[103]/PH4 MA0/SCK_1/GPIO[20]/PB4 FABM/MA1/SOUT_1/GPIO[21]/PB5 VDDE_B VSSE_B ABS[0]/MA2/SIN_1/GPIO[22]/PB6 VDD12 VSS12 VDDA VSSA XTAL32/ANS15/GPIO[45]/PC15 EXTAL32/ANS14/GPIO[44]/PC14 PCS0_1/MA2/ANS13/GPIO[43]/PC13 PCS1_1/MA1/ANS12/GPIO[42]/PC12 PCS2_1/MA0/ANS11/GPIO[41]/PC11 SOUND/ANS10(mux)/GPIO[40]/PC10 ANS9/GPIO[39]/PC9 ANS8/GPIO[38]/PC8 VDDE_C VSSE_C ANS7/GPIO[37]/PC7 ANS6/GPIO[36]/PC6 ANS5/GPIO[35]/PC5 ANS4/GPIO[34]/PC4 ANS3/GPIO[33]/PC3 ANS2/GPIO[32]/PC2 ANS1/GPIO[31]/PC1 ANS0/GPIO[30]/PC0
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Figure 5. 176-pin LQFP Pinout
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor
2.3
208 MAPBGA package ballmap
CAUTION
Any pins labeled "NC" must not be connected to any external circuit.
1 2 PJ0 VDDE_A PA3 PA5 PA7 PA9 PA11 PA13 PA14 VDDE_A VDDPLL VPP VLCD PH1 VDDE_B MSEO 3 PJ1 PJ2 VDDE_A PG0 PG1 PG3 PG5 PA15 PG8 PG9 NMI/PF2 PH3 PH2 VDDE_B EVTO EVTI 4 PJ3 PJ4 PJ9 VDD12 PG2 PG4 PG6 PG7 PG10 PG11 MDO3 VREG BYPASS VDD12 MDO2 PF9 PF8 PK11 MDO1 PH4 MDO0 PK10 PB13 PB12 PB9 PB8 PB7 PB6 VDDE_C PB5 PB4 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 VSSA PC6 PC5 PC4 VDDA PB11 PC3 PC2 PC1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 5 PJ5 PJ6 PJ10 PJ11 6 PJ7 PJ8 PJ12 PJ13 7 PJ14 PJ15 PK0 PK1 8 PF0 PF1 PF3 PF4 9 PF5 PF6 PF7 VDD12 10 PK9 NC NC PG12 11 PK5 PK6 PK7 PK8 12 NC PK2 PK3 PK4 13 NC NC NC VDD12 NC NC NC PE5 PE4 PE3 PD15 PD14 VDDMA PB10 PB3 PC0 14 PF10 NC VDDE_E NC NC NC PE7 PE6 PE2 PD13 PD12 PD11 PD10 NC PB2 PB1 15 PF11 VDDE_E NC NC NC NC PE1 VDDMC PE0 PD9 VDDMB PD5 PD4 PD2 VDDE_B PB0 16 PF12 PF13 PF14 PF15 NC NC NC VSSMC PD8 PD7 VSSMB PD6 PD3 PD1 PD0 VSSMA
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 29
Figure 6 shows the ballmap for the 208-pin BGA package.
A B C D E F G H J K L M N P R T
PA0 PA1 PA2 PA4 PA6 PA8 PA10 PA12 RESET XTAL VSSPLL EXTAL VDDR VRC_ CTRL PH0 MCKO
Figure 6. 208-pin MAPBGA pinout
2.4
Pad configuration during reset phases
All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate. After power-up phase, all pads are floating with the following exceptions: * * * * * PB[5] (FAB) is pull-down. Without external strong pullup the device starts fetching from flash. RESET pad is driven low. This is released only after PHASE2 reset completion. Main oscillator pads (EXTAL, XTAL) are tristate. Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output. The following pads are pullup: -- PB[6] -- PH[0] -- PH[1] -- PH[3] -- EVTI
2.5
Voltage supply pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization. There is a preferred power-up sequence for devices in the MPC5606S family. That sequence is described in the following paragraphs. Broadly, the supply voltages can be grouped as follows: * * VREG HV supply (VDDR) Generic IO supply or noise free supply -- VDDA -- VDDE_A -- VDDE_B -- VDDE_C -- VDDE_E -- VDDMA -- VDDMB -- VDDMC -- VDDPLL LV supply (VDD12) Generic IO supply or noise free supply VREG HV supply (VDDR - Should be the last HV supply to ramp up. It is also OK if all HV supplies including VDDR ramp up together) LV supply
* 1. 2. 3.
The preferred order of ramp up is as follows:
The reason for following this sequence is to ensure that when VREG releases its LVDs, the I/O and other HV segments are powered properly. This is important because the MPC5606S does not monitor LVDs on I/O HV supplies.
MPC5606S Microcontroller Data Sheet, Rev. 6 30 Freescale Semiconductor
Table 5. Voltage supply pin descriptions
Pin number Supply Pin VDD121 VDDA VDDE_A VDDE_B VDDE_C VDDE_E VDDMA
2
Function 144 LQFP 1.2 V core supply 3.3 V/5 V ADC supply source 3.3 V/5 V I/O supply 3.3 V/5 V I/O supply 3.3 V/5 V I/O supply 3.3 V/5 V I/O supply Motor pads 5 V supply Motor pads 5 V supply Motor pads 5 V supply 1.2 V PLL supply VREG reg supply 9 V - 12 V flash test analog write signal Digital ground ADC ground Stepper motor ground Stepper motor ground Stepper motor ground MHz oscillator ground PLL ground 42, 51, 103, 118, 133 53 7, 124 38 63 109 77 87 97 31 22 26 8, 23, 39, 43, 52, 64, 104, 110, 119, 125, 134 54 78 88 98 28 30 176 LQFP 50, 67, 123, 148, 163 69 7, 154, 170 46, 64 79 133 93 103 113 31 22 26 8, 23, 47, 51, 68, 80, 124, 134, 149, 155, 164, 65, 171 70 94 104 114 28 30
VDDMB2 VDDMC2 VDDPLL VDDR VPP
3
VSS VSSA VSSMA VSSMB VSSMC VSSOSC VSSPLL
1 2
Decoupling capacitors must be connected between these pins and the nearest VSS12 pin. All stepper motor supplies need to be at same level (3.3 V or 5 V). 3 This signal needs to be connected to ground during normal operation.
2.6
* * * *
Pad types
The port pin summary table The pad type descriptions The description of the pad configuration registers in the SIUL chapter of the device reference manual The device data sheet
The pads available for system pins and functional port pins are described in:
2.7
System pins
The system pins are listed in Table 6.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 31
Table 6. System pin descriptions
Pin No. System pin Function I/O direction I/O Pad type M RESET config Input, weak pull up 144 LQFP 176 LQFP 24 24 208 MAPBG A J1
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise filter. Analog output of the oscillator amplifier circuit. Input for the clock generator in bypass mode. Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator bypass mode is used.
EXTAL
X
-
29
29
M1
XTAL
I
X
-
27
27
K1
VRC_CTRL VREG ballast control gain VREG_ BYPASS1
1
25 I X 32
25 32
P1 M4
Pin used for factory testing
VREG_BYPASS should be pulled down externally.
2.8
Debug pins
Table 7. Debug pin descriptions
Pin number Debug pin Function Pad type M1 M1 F M1 M1 M1 M1 M1 I/O direction I/O I/O I/O I/O I/O I/O I/O I/O RESET config 144 LQFP Input, Pull Up Input, Pull Up Input, Pull Up Input, Pull Up Input, Pull Up Input, Pull Up Input, Pull Up Input, Pull Up -- -- -- -- -- -- -- -- 176 LQFP 208 MAPB 1 GA 37 35 33 38 40 42 44 34 T3 R3 T1 T5 P5 P4 L4 T2
The debug pins are listed in Table 7.
EVTI EVTO MCKO MDO0 MDO1 MDO2 MDO3 MSEO
Nexus event input Nexus event output Nexus message clock output Nexus message clock output Nexus message clock output Nexus message clock output Nexus message clock output Nexus message clock output
MPC5606S Microcontroller Data Sheet, Rev. 6 32 Freescale Semiconductor
1
On the 176-pin package, the debug pins are multiplexed with other pins. The multiplexing is described in the port pin summary table.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 33
2.9
Port pin summary
Table 8. Port pin summary
Pin number Port pin PA[0] PCR Alternate register function1 PCR[0] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function Special function2 FP23 Peripheral3 I/O Pad RESET direction type4 config.5 I/O M1 None, None 144 LQFP 135 176 LQFP 165 208 MAPBG A A1
34 MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor
The functional port pins are listed in Table 8.
GPIO[0] DCU_R0 eMIOSA[22] SOUND GPIO[1] DCU_R1 eMIOSA[21] -- GPIO[2] DCU_R2 eMIOSA[20] -- GPIO[3] DCU_R3 eMIOSA[19] -- GPIO[4] DCU_R4 eMIOSA[18] -- GPIO[5] DCU_R5 eMIOSA[17] -- GPIO[6] DCU_R6 eMIOSA[15] --
SIUL DCU PWM/Timer Sound SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer --
PA[1]
PCR[1]
FP22
I/O
M1
None, None
136
166
B1
PA[2]
PCR[2]
FP21
I/O
M1
None, None
137
167
C1
PA[3]
PCR[3]
FP20
I/O
M1
None, None
138
168
C2
PA[4]
PCR[4]
FP19
I/O
M1
None, None
139
169
D1
PA[5]
PCR[5]
FP18
I/O
M1
None, None
140
172
D2
PA[6]
PCR[6]
FP17
I/O
M1
None, None
141
173
E1
Table 8. Port pin summary (continued)
Pin number Port pin PA[7] PCR Alternate register function1 PCR[7] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function Special function2 FP16 Peripheral
3
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 35
I/O Pad RESET direction type4 config.5 I/O M1 None, None
144 LQFP 142
176 LQFP 174
208 MAPBG A E2
GPIO[7] DCU_R7 eMIOSA[16] -- GPIO[8] DCU_G0 eMIOSB[23] SCL_2 GPIO[9] DCU_G1 eMIOSB[18] SDA_2 GPIO[10] DCU_G2 eMIOSB[20] -- GPIO[11] DCU_G3 eMIOSA[13] -- GPIO[12] DCU_G4 eMIOSA[12] -- GPIO[13] DCU_G5 eMIOSA[11] -- GPIO[14] DCU_G6 eMIOSA[10] --
SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer I2C_2 SIUL DCU PWM/Timer I2C_2 SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer --
PA[8]
PCR[8]
FP15
I/O
M1
None, None
143
175
F1
PA[9]
PCR[9]
FP14
I/O
M1
None, None
144
176
F2
PA[10] PCR[10] Option 0 Option 1 Option 2 Option 3 PA[11] PCR[11] Option 0 Option 1 Option 2 Option 3 PA[12] PCR[12] Option 0 Option 1 Option 2 Option 3 PA[13] PCR[13] Option 0 Option 1 Option 2 Option 3 PA[14] PCR[14] Option 0 Option 1 Option 2 Option 3
FP13
I/O
M1
None, None
1
1
G1
FP12
I/O
M1
None, None
2
2
G2
FP11
I/O
M1
None, None
3
3
H1
FP10
I/O
M1
None, None
4
4
H2
FP9
I/O
M2
None, None
5
5
J2
Table 8. Port pin summary (continued)
Pin number Port pin PCR Alternate register function1 Function Special function2 FP8 Peripheral
3
36 PA[15] PCR[15] Option 0 Option 1 Option 2 Option 3 PB[0] PCR[16] Option 0 Option 1 Option 2 Option 3 PCR[17] Option 0 Option 1 Option 2 Option3 PCR[18] Option 0 Option 1 Option 2 Option3 PCR[19] Option 0 Option 1 Option 2 Option3 PCR[20] Option 0 Option 1 Option 2 Option 3 PCR[21] Option 0 Option 1 Option 2 Option 3 PCR[22] Option 0 Option 1 Option 2 Option 3 GPIO[15] DCU_G7 eMIOSA[9] -- GPIO[16] CANTX_0 PDI1 -- GPIO[17] CANRX_0 PDI0 -- GPIO[18] TXD_0 -- -- GPIO[19] RXD_0 -- -- GPIO[20] SCK_1 MA0 -- GPIO[21] SOUT_1 MA1 FABM GPIO[22] SIN_1 MA2 ABS[0] PB[1] MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor PB[2] PB[3] PB[4] PB[5] PB[6]
I/O Pad RESET direction type4 config.5 I/O M1 None, None
144 LQFP 6
176 LQFP 6
208 MAPBG A H3
SIUL DCU PWM/Timer -- SIUL FlexCAN_0 PDI -- SIUL FlexCAN_0 PDI -- SIUL LINFlex_0 -- -- SIUL LINFlex_0 -- -- SIUL DSPI_1 ADC -- SIUL DSPI_1 ADC Control SIUL DSPI_1 ADC Control
--
I/O
M1
None, None
106
130
T15
--
I/O
S
None, None
105
129
T14
--
I/O
S
None, None
112
140
R14
--
I/O
S
None, None
111
139
R13
--
I/O
M1
None, None
48
62
P8
--
I/O
M1
Input, Pulldow n Input, Pullup
49
63
N8
--
I/O
S
50
66
R7
Table 8. Port pin summary (continued)
Pin number Port pin PB[7] PCR Alternate register function1 PCR[23] Option 0 Option 1 Option 2 Option 3 PCR[24] Option 0 Option 1 Option 2 Option 3 PCR[25] Option 0 Option 1 Option 2 Option 3 Function Special function2 -- Peripheral
3
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 37
I/O Pad RESET direction type4 config.5 I/O S None, None
144 LQFP 46
176 LQFP 56
208 MAPBG A P7
GPIO[23] SIN_0 eMIOSB[22] -- GPIO[24] SOUT_0 eMIOSB[21] -- GPIO[25] SCK_0 eMIOSB[20] -- GPIO[26] CANRX_1 PDI2 eMIOSA[23] GPIO[27] CANTX_1 PDI3 eMIOSA[16] GPIO[28] RXD_1 eMIOSB[19] PCS2_0 GPIO[29] TXD_1 eMIOSB[18] PCS1_0 Reserved Reserved GPIO[30] -- -- --
SIUL DSPI_0 PWM/Timer -- SIUL DSPI_0 PWM/Timer -- SIUL DSPI_0 PWM/Timer -- SIUL FlexCAN_1 PDI PWM/Timer SIUL FlexCAN_1 PDI PWM/Timer SIUL LINFlex_1 PWM/Timer DSPI_0 SIUL LINFlex_1 PWM/Timer DSPI_0 -- -- SIUL -- -- --
PB[8]
--
I/O
M1
None, None
45
55
N7
PB[9]
--
I/O
M1
None, None
44
54
T6
PB[10] PCR[26] Option 0 Option 1 Option 2 Option 3 PB[11] PCR[27] Option 0 Option 1 Option 2 Option 3 PB[12] PCR[28] Option 0 Option 1 Option 2 Option 3 PB[13] PCR[29] Option 0 Option 1 Option 2 Option 3 PB[14] PB[15] PC[0] -- -- -- --
--
I/O
S
None, None
107
131
P13
--
I/O
M1
None, None
108
132
N12
--
I/O
S
None, None
40
48
R6
--
I/O
S
None, None
41
49
P6
-- -- ANS[0]
-- -- I/O
-- -- J
-- -- None, None
-- -- 72
-- -- 88
-- -- T13
PCR[30] Option 0 Option 1 Option 2 Option 3
Table 8. Port pin summary (continued)
Pin number Port pin PC[1] PCR Alternate register function1 PCR[31] Option 0 Option 1 Option 2 Option 3 PCR[32] Option 0 Option 1 Option 2 Option 3 PCR[33] Option 0 Option 1 Option 2 Option 3 PCR[34] Option 0 Option 1 Option 2 Option 3 PCR[35] Option 0 Option 1 Option 2 Option 3 PCR[36] Option 0 Option 1 Option 2 Option 3 PCR[37] Option 0 Option 1 Option 2 Option 3 PCR[38] Option 0 Option 1 Option 2 Option 3 Function Special function2 ANS[1] Peripheral
3
38 GPIO[31] -- -- -- GPIO[32] -- -- -- GPIO[33] -- -- -- GPIO[34] -- -- -- GPIO[35] -- -- -- GPIO[36] -- -- -- GPIO[37] -- -- -- GPIO[38] -- -- -- PC[2] PC[3] MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor PC[4] PC[5] PC[6] PC[7] PC[8]
I/O Pad RESET direction type4 config.5 I/O J None, None
144 LQFP 71
176 LQFP 87
208 MAPBG A T12
SIUL -- -- -- SIUL -- -- -- SIUL -- -- -- SIUL -- -- -- SIUL -- -- -- SIUL -- -- -- SIUL -- -- -- SIUL -- -- --
ANS[2]
I/O
J
None, None
70
86
R12
ANS[3]
I/O
J
None, None
69
85
P12
ANS[4]
I/O
J
None, None
68
84
R11
ANS[5]
I/O
J
None, None
67
83
P11
ANS[6]
I/O
J
None, None
66
82
N11
ANS[7]
I/O
J
None, None
65
81
R10
ANS[8]
I/O
J
None, None
62
78
P10
Table 8. Port pin summary (continued)
Pin number Port pin PC[9] PCR Alternate register function1 PCR[39] Option 0 Option 1 Option 2 Option 3 Function Special function2 ANS[9] Peripheral
3
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 39
I/O Pad RESET direction type4 config.5 I/O J None, None
144 LQFP 61
176 LQFP 77
208 MAPBG A N10
GPIO[39] -- -- -- GPIO[40] -- SOUND -- GPIO[41] -- MA0 PCS2_1 GPIO[42] -- MA1 PCS1_1 GPIO[43] -- MA2 PCS0_1 GPIO[44] -- -- -- GPIO[45] -- -- -- GPIO[46] M0C0M SSD0_0 eMIOSB[23]
SIUL -- -- -- SIUL -- SGL -- SIUL -- ADC DSPI_1 SIUL -- ADC DSPI_1 SIUL -- ADC DSPI_1
PC[10] PCR[40] Option 0 Option 1 Option 2 Option 3 PC[11] PCR[41] Option 0 Option 1 Option 2 Option 3 PC[12] PCR[42] Option 0 Option 1 Option 2 Option 3 PC[13] PCR[43] Option 0 Option 1 Option 2 Option 3 PC[14] PCR[44] Option 0 Option 1 Option 2 Option 3 PC[15] PCR[45] Option 0 Option 1 Option 2 Option 3 PD[0] PCR[46] Option 0 Option 1 Option 2 Option 3
ANS[10]
I/O
J
None, None
60
76
T9
ANS[11]
I/O
J
None, None
59
75
R9
ANS[12]
I/O
J
None, None
58
74
P9
ANS[13]
I/O
J
None, None
57
73
N9
ANS[14] SIUL EXTAL32 -- -- -- ANS[15] XTAL32 SIUL -- -- -- SIUL SMC SSD PWM/Timer
I/O
J
None, None
56
72
T8
I/O
J
None, None
55
71
R8
--
I/O
SMD
None, None
73
89
R16
Table 8. Port pin summary (continued)
Pin number Port pin PD[1] PCR Alternate register function1 PCR[47] Option 0 Option 1 Option 2 Option 3 PCR[48] Option 0 Option 1 Option 2 Option 3 PCR[49] Option 0 Option 1 Option 2 Option 3 PCR[50] Option 0 Option 1 Option 2 Option 3 PCR[51] Option 0 Option 1 Option 2 Option 3 PCR[52] Option 0 Option 1 Option 2 Option 3 PCR[53] Option 0 Option 1 Option 2 Option 3 PCR[54] Option 0 Option 1 Option 2 Option 3 Function Special function2 -- Peripheral
3
40 GPIO[47] M0C0P SSD0_1 eMIOSB[22] GPIO[48] M0C1M SSD0_2 eMIOSB[21] GPIO[49] M0C1P SSD0_3 eMIOSB[20] GPIO[50] M1C0M SSD1_0 eMIOSB[19] GPIO[51] M1C0P SSD1_1 eMIOSB[18] GPIO[52] M1C1M SSD1_2 eMIOSB[17] GPIO[53] M1C1P SSD1_3 eMIOSB[16] GPIO[54] M2C0M SSD2_0 -- PD[2] PD[3] MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor PD[4] PD[5] PD[6] PD[7] PD[8]
I/O Pad RESET direction type4 config.5 I/O SMD None, None
144 LQFP 74
176 LQFP 90
208 MAPBG A P16
SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD --
--
I/O
SMD
None, None
75
91
P15
--
I/O
SMD
None, None
76
92
N16
--
I/O
SMD
None, None
79
95
N15
--
I/O
SMD
None, None
80
96
M15
--
I/O
SMD
None, None
81
97
M16
--
I/O
SMD
None, None
82
98
K16
--
I/O
SMD
None, None
83
99
J16
Table 8. Port pin summary (continued)
Pin number Port pin PD[9] PCR Alternate register function1 PCR[55] Option 0 Option 1 Option 2 Option 3 Function Special function2 -- Peripheral
3
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 41
I/O Pad RESET direction type4 config.5 I/O SMD None, None
144 LQFP 84
176 LQFP 100
208 MAPBG A K15
GPIO[55] M2C0P SSD2_1 -- GPIO[56] M2C1M SSD2_2 -- GPIO[57] M2C1P SSD2_3 -- GPIO[58] M3C0M SSD3_0 -- GPIO[59] M3C0P SSD3_1 -- GPIO[60] M3C1M SSD3_2 -- GPIO[61] M3C1P SSD3_3 -- GPIO[62] M4C0M SSD4_0 eMIOSA[15]
SIUL SMC SSD -- SIUL SMC SSD -- SIUL SMC SSD -- SIUL SMC SSD -- SIUL SMC SSD -- SIUL SMC SSD -- SIUL SMC SSD -- SIUL SMC SSD PWM/Timer
PD[10] PCR[56] Option 0 Option 1 Option 2 Option 3 PD[11] PCR[57] Option 0 Option 1 Option 2 Option 3 PD[12] PCR[58] Option 0 Option 1 Option 2 Option 3 PD[13] PCR[59] Option 0 Option 1 Option 2 Option 3 PD[14] PCR[60] Option 0 Option 1 Option 2 Option 3 PD[15] PCR[61] Option 0 Option 1 Option 2 Option 3 PE[0] PCR[62] Option 0 Option 1 Option 2 Option 3
--
I/O
SMD
None, None
85
101
N14
--
I/O
SMD
None, None
86
102
M14
--
I/O
SMD
None, None
89
105
L14
--
I/O
SMD
None, None
90
106
K14
--
I/O
SMD
None, None
91
107
M13
--
I/O
SMD
None, None
92
108
L13
--
I/O
SMD
None, None
93
109
J15
Table 8. Port pin summary (continued)
Pin number Port pin PE[1] PCR Alternate register function1 PCR[63] Option 0 Option 1 Option 2 Option 3 PCR[64] Option 0 Option 1 Option 2 Option 3 PCR[65] Option 0 Option 1 Option 2 Option 3 PCR[66] Option 0 Option 1 Option 2 Option 3 PCR[67] Option 0 Option 1 Option 2 Option 3 PCR[68] Option 0 Option 1 Option 2 Option 3 PCR[69] Option 0 Option 1 Option 2 Option 3 -- -- -- -- -- -- -- -- -- -- Function Special function2 -- Peripheral
3
42 GPIO[63] M4C0P SSD4_1 eMIOSA[14] GPIO[64] M4C1M SSD4_2 eMIOSA[13] GPIO[65] M4C1P SSD4_3 eMIOSA[12] GPIO[66] M5C0M SSD5_0 eMIOSA[11] GPIO[67] M5C0P SSD5_1 eMIOSA[10] GPIO[68] M5C1M SSD5_2 eMIOSA[9] GPIO[69] M5C1P SSD5_3 eMIOSA[8] Reserved Reserved Reserved Reserved Reserved PE[2] PE[3] MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor PE[4] PE[5] PE[6] PE[7] PE[8] PE[9] PE[10] PE[11] PE[12]
I/O Pad RESET direction type4 config.5 I/O SMD None, None
144 LQFP 94
176 LQFP 110
208 MAPBG A G15
SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer SIUL SMC SSD PWM/Timer -- -- -- -- --
--
I/O
SMD
None, None
95
111
J14
--
I/O
SMD
None, None
96
112
K13
--
I/O
SMD
None, None
99
115
J13
--
I/O
SMD
None, None
100
116
H13
--
I/O
SMD
None, None
101
117
H14
--
I/O
SMD
None, None
102
118
G14
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
Table 8. Port pin summary (continued)
Pin number Port pin PE[13] PE[14] PE[15] PF[0] PCR Alternate register function1 -- -- -- -- -- -- Function Special function2 -- -- -- FP39 Peripheral
3
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 43
I/O Pad RESET direction type4 config.5 -- -- -- I/O -- -- -- S -- -- -- None, None
144 LQFP -- -- -- 113
176 LQFP -- -- -- 143
208 MAPBG A -- -- -- A8
Reserved Reserved Reserved GPIO[70] eMIOSA[13] PDI4 eMIOSA[22] GPIO[71] eMIOSA[12] PDI5 eMIOSA[21] GPIO[72] NMI -- -- GPIO[73] eMIOSA[11] PDI6 -- GPIO[74] eMIOSA[10] PDI7 -- GPIO[75] eMIOSA[9] DCU_TAG -- GPIO[76] SDA_0 -- --
-- -- -- SIUL PWM/Timer PDI PWM/Timer SIUL PWM/Timer PDI PWM/Timer SIUL NMI -- -- SIUL PWM/Timer PDI -- SIUL PWM/Timer PDI -- SIUL PWM/Timer DCU -- SIUL I2C_0 -- --
PCR[70] Option 0 Option 1 Option 2 Option 3 PCR[71] Option 0 Option 1 Option 2 Option 3 PCR[72] Option 0 Option 1 Option 2 Option 3 PCR[73] Option 0 Option 1 Option 2 Option 3 PCR[74] Option 0 Option 1 Option 2 Option 3 PCR[75] Option 0 Option 1 Option 2 Option 3 PCR[76] Option 0 Option 1 Option 2 Option 3
PF[1]
FP38
I/O
S
None, None
114
144
B8
PF[2]
--
I/O
S
None, None
37
45
L3
PF[3]
FP37
I/O
M1
None, None
115
145
C8
PF[4]
FP36
I/O
M1
None, None
116
146
D8
PF[5]
FP35
I/O
M1
None, None
117
147
A9
PF[6]
FP34
I/O
S
None, None
120
150
B9
Table 8. Port pin summary (continued)
Pin number Port pin PF[7] PCR Alternate register function1 PCR[77] Option 0 Option 1 Option 2 Option 3 PCR[78] Option 0 Option 1 Option 2 Option 3 PCR[79] Option 0 Option 1 Option 2 Option 3 Function Special function2 FP33 Peripheral
3
44 GPIO[77] SCL_0 PCS2_1 -- GPIO[78] SDA_1 PCS1_1 RXD_1 GPIO[79] SCL_1 PCS0_1 TXD_1 GPIO[80] eMIOSA[16] PCS0_2 -- GPIO[81] eMIOSB[23] IO2/PCS1_26 -- GPIO[82] eMIOSB[16] IO3/PCS2_26 -- GPIO[83] IO0/SIN_26 CANRX_1 -- GPIO[84] IO1/SOUT_26 CANTX_1 -- PF[8] PF[9] MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor PF[10] PCR[80] Option 0 Option 1 Option 2 Option 3 PF[11] PCR[81] Option 0 Option 1 Option 2 Option 3 PF[12] PCR[82] Option 0 Option 1 Option 2 Option 3 PF[13] PCR[83] Option 0 Option 1 Option 2 Option 3 PF[14] PCR[84] Option 0 Option 1 Option 2 Option 3
I/O Pad RESET direction type4 config.5 I/O S None, None
144 LQFP 121
176 LQFP 151
208 MAPBG A C9
SIUL I2C_0 DSPI_1 -- SIUL I2C_1 DSPI_1 LINFlex_1 SIUL I2C_1 DSPI_1 LINFlex_1 SIUL PWM/Timer QuadSPI -- SIUL PWM/Timer QuadSPI -- SIUL PWM/Timer QuadSPI -- SIUL QuadSPI FlexCAN_1 -- SIUL QuadSPI FlexCAN_1 --
FP32
I/O
S
None, None
122
152
T4
FP31
I/O
S
None, None
123
153
R4
FP29
I/O
M1
None, None
127
157
A14
FP28
I/O
M1
None, None
128
158
A15
FP27
I/O
M1
None, None
129
159
A16
FP26
I/O
M1
None, None
130
160
B16
FP25
I/O
M1
None, None
131
161
C16
Table 8. Port pin summary (continued)
Pin number Port pin PCR Alternate register function1 Function Special function2 FP24 Peripheral
3
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 45
I/O Pad RESET direction type4 config.5 I/O F None, None
144 LQFP 132
176 LQFP 162
208 MAPBG A D16
PF[15] PCR[85] Option 0 Option 1 Option 2 Option 3 PG[0] PCR[86] Option 0 Option 1 Option 2 Option 3 PCR[87] Option 0 Option 1 Option 2 Option 3 PCR[88] Option 0 Option 1 Option 2 Option 3 PCR[89] Option 0 Option 1 Option 2 Option 3 PCR[90] Option 0 Option 1 Option 2 Option 3 PCR[91] Option 0 Option 1 Option 2 Option 3 PCR[92] Option 0 Option 1 Option 2 Option 3
GPIO[85] SCK_2 -- -- GPIO[86] DCU_B0 SCL_3 SOUND GPIO[87] DCU_B1 SDA_3 -- GPIO[88] DCU_B2 eMIOSB[19] -- GPIO[89] DCU_B3 eMIOSB[21] -- GPIO[90] DCU_B4 eMIOSB[17] -- GPIO[91] DCU_B5 eMIOSA[8] -- GPIO[92] DCU_B6 -- --
SIUL QuadSPI -- -- SIUL DCU I2C_3 SGL SIUL DCU I2C_3 -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU PWM/Timer -- SIUL DCU -- --
FP7
I/O
M2
None, None
9
9
D3
PG[1]
FP6
I/O
M1
None, None
10
10
E3
PG[2]
FP5
I/O
M2
None, None
11
11
E4
PG[3]
FP4
I/O
M1
None, None
12
12
F3
PG[4]
FP3
I/O
M2
None, None
13
13
F4
PG[5]
FP2
I/O
M1
None, None
14
14
G3
PG[6]
FP1
I/O
M2
None, None
15
15
G4
Table 8. Port pin summary (continued)
Pin number Port pin PG[7] PCR Alternate register function1 PCR[93] Option 0 Option 1 Option 2 Option 3 PCR[94] Option 0 Option 1 Option 2 Option 3 PCR[95] Option 0 Option 1 Option 2 Option 3 Function Special function2 FP0 Peripheral
3
46 GPIO[93] DCU_B7 -- -- GPIO[94] DCU_VSYNC -- -- GPIO[95] DCU_HSYNC -- -- GPIO[96] DCU_DE -- -- GPIO[97] DCU_PCLK -- -- GPIO[98] eMIOSA[23] SOUND eMIOSA[8] Reserved Reserved Reserved GPIO[99] TCK -- -- PG[8] PG[9] MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor PG[10] PCR[96] Option 0 Option 1 Option 2 Option 3 PG[11] PCR[97] Option 0 Option 1 Option 2 Option 3 PG[12] PCR[98] Option 0 Option 1 Option 2 Option 3 PG[13] PG[14] PG[15] -- -- -- -- -- -- PH[0]7 PCR[99] Option 0 Option 1 Option 2 Option 3
I/O Pad RESET direction type4 config.5 I/O M1 None, None
144 LQFP 16
176 LQFP 16
208 MAPBG A H4
SIUL DCU -- -- SIUL DCU -- -- SIUL DCU -- -- SIUL DCU -- -- SIUL DCU -- -- SIUL PWM/Timer SGL PWM/Timer -- -- -- SIUL JTAG -- --
BP0
I/O
M2
Input, None
17
17
J3
BP1
I/O
M1
Input, None
18
18
K3
BP2
I/O
M2
None, None
19
19
J4
BP3
I/O
M1
None, None
20
20
K4
FP30
I/O
S
None, None
126
156
D10
-- -- -- --
-- -- -- I/O
-- -- -- S
-- -- -- Input, Pullup
-- -- -- 36
-- -- -- 43
-- -- -- R1
Table 8. Port pin summary (continued)
Pin number Port pin PCR Alternate register function1 Function Special function2 -- Peripheral
3
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 47
I/O Pad RESET direction type4 config.5 I/O S Input, Pullup
144 LQFP 33
176 LQFP 36
208 MAPBG A P2
PH[1]7 PCR[100] Option 0 Option 1 Option 2 Option 3 PH[2]7 PCR[101] Option 0 Option 1 Option 2 Option 3 PH[3]7 PCR[102] Option 0 Option 1 Option 2 Option 3 PH[4] PCR[103] Option 0 Option 1 Option 2 Option 3 PH[5] PCR[104] Option 0 Option 1 Option 2 Option 3 PH[6] PH[7] PH[8] PH[9] PH[10] PH[11] PH[12] PH[13] PH[14] PH[15] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
GPIO[100] TDI -- -- GPIO[101] TDO -- -- GPIO[102] TMS -- -- GPIO[103] PCS0_0 eMIOSB[16] CLKOUT GPIO[104] VLCD8 -- -- Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SIUL JTAG -- -- SIUL JTAG -- -- SIUL JTAG -- -- SIUL DSPI_0 PWM/Timer Control SIUL LCD -- -- -- -- -- -- -- -- -- -- -- --
--
I/O
M1
Output, None
34
39
N3
--
I/O
S
Input, Pullup
35
41
M3
--
I/O
F
None, None
47
61
R5
--
I/O
S
None, None
21
21
N2
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
Table 8. Port pin summary (continued)
Pin number Port pin PCR Alternate register function1 Function Special function2 -- Peripheral
3
48 PJ[0] PCR[105] Option 0 Option 1 Option 2 Option 3 PJ[1] PCR[106] Option 0 Option 1 Option 2 Option 3 PJ[2] PCR[107] Option 0 Option 1 Option 2 Option 3 PJ[3] PCR[108] Option 0 Option 1 Option 2 Option 3 PJ[4] PCR[109] Option 0 Option 1 Option 2 Option 3 PJ[5] PCR[110] Option 0 Option 1 Option 2 Option 3 PJ[6] PCR[111] Option 0 Option 1 Option 2 Option 3 PJ[7] PCR[112] Option 0 Option 1 Option 2 Option 3 GPIO[105] PDI_DE -- -- GPIO[106] PDI_HSYNC -- -- GPIO[107] PDI_VSYNC -- -- GPIO[108] PDI_PCLK -- -- GPIO[109] PDI[0] CANRX_0 -- GPIO[110] PDI[1] CANTX_0 -- GPIO[111] PDI[2] CANRX_1 eMIOSA[22] GPIO[112] PDI[3] CANTX_1 eMIOSA[21] MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor
I/O Pad RESET direction type4 config.5 I/O S None, None
144 LQFP --
176 LQFP 119
208 MAPBG A A2
SIUL PDI -- -- SIUL PDI -- -- SIUL PDI -- -- SIUL PDI -- -- SIUL PDI FlexCAN_0 -- SIUL PDI FlexCAN_0 -- SIUL PDI FlexCAN_1 PWM/Timer SIUL PDI FlexCAN_1 PWM/Timer
--
I/O
S
None, None
--
120
A3
--
I/O
S
None, None
--
121
B3
--
I/O
M1
None, None
--
122
A4
--
I/O
S
None, None
--
57
B4
--
I/O
M1
None, None
--
58
A5
--
I/O
S
None, None
--
59
B5
--
I/O
M1
None, None
--
60
A6
Table 8. Port pin summary (continued)
Pin number Port pin PCR Alternate register function1 Function Special function2 -- Peripheral
3
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 49
I/O Pad RESET direction type4 config.5 I/O S None, None
144 LQFP --
176 LQFP 125
208 MAPBG A B6
PJ[8] PCR[113] Option 0 Option 1 Option 2 Option 3 PJ[9] PCR[114] Option 0 Option 1 Option 2 Option 3 PJ[10] PCR[115] Option 0 Option 1 Option 2 Option 3 PJ[11] PCR[116] Option 0 Option 1 Option 2 Option 3 PJ[12] PCR[117] Option 0 Option 1 Option 2 Option 3 PJ[13] PCR[118] Option 0 Option 1 Option 2 Option 3 PJ[14] PCR[119] Option 0 Option 1 Option 2 Option 3 PJ[15] PCR[120] Option 0 Option 1 Option 2 Option 3
GPIO[113] PDI[4] -- -- GPIO[114] PDI[5] -- -- GPIO[115] PDI[6] -- -- GPIO[116] PDI[7] -- -- GPIO[117] PDI[8] eMIOSB[17] -- GPIO[118] PDI[9] eMIOSB[20] -- GPIO[119] PDI[10] eMIOSA[20] -- GPIO[120] PDI[11] eMIOSA[19] --
SIUL PDI -- -- SIUL PDI -- -- SIUL PDI -- -- SIUL PDI -- -- SIUL PDI PWM/Timer -- SIUL PDI PWM/Timer -- SIUL PDI PWM/Timer -- SIUL PDI PWM/Timer --
--
I/O
S
None, None
--
126
C4
--
I/O
S
None, None
--
127
C5
--
I/O
S
None, None
--
128
D5
--
I/O
M1
None, None
--
135
C6
--
I/O
M1
None, None
--
136
D6
--
I/O
M1
None, None
--
137
A7
--
I/O
M1
None, None
--
138
B7
Table 8. Port pin summary (continued)
Pin number Port pin PCR Alternate register function1 Function Special function2 -- Peripheral
3
50 PK[0] PCR[121] Option 0 Option 1 Option 2 Option 3 PK[1] PCR[122] Option 0 Option 1 Option 2 Option 3 PK[2] PCR[123] Option 0 Option 1 Option 2 Option 3 PK[3] PCR[124] Option 0 Option 1 Option 2 Option 3 PK[4] PCR[125] Option 0 Option 1 Option 2 Option 3 PK[5] PCR[126] Option 0 Option 1 Option 2 Option 3 PK[6] PCR[127] Option 0 Option 1 Option 2 Option 3 PK[7] PCR[128] Option 0 Option 1 Option 2 Option 3 GPIO[121] PDI[12] eMIOSA[18] DCU_TAG GPIO[122] PDI[13] eMIOSA[17] -- GPIO[123] MCKO PDI[10] -- GPIO[124] MSEO PDI[11] -- GPIO[125] EVTO PDI[12] -- GPIO[126] EVTI PDI[13] -- GPIO[127] MDO0 PDI[14] -- GPIO[128] MDO1 PDI[15] -- MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor
I/O Pad RESET direction type4 config.5 I/O M1 None, None
144 LQFP --
176 LQFP 141
208 MAPBG A C7
SIUL PDI PWM/Timer DCU SIUL PDI PWM/Timer -- SIUL Nexus PDI -- SIUL Nexus PDI -- SIUL Nexus PDI -- SIUL Nexus PDI -- SIUL Nexus PDI -- SIUL Nexus PDI --
--
I/O
M1
None, None
--
142
D7
--
I/O
F
None, None
--
33
B12
--
I/O
M1
None, None
--
34
C12
--
I/O
M1
None, None
--
35
D12
--
I/O
M1
None, None
--
37
A11
--
I/O
M1
None, None
--
38
B11
--
I/O
M1
None, None
--
40
C11
Table 8. Port pin summary (continued)
Pin number Port pin PCR Alternate register function1 Function Special function2 -- Peripheral
3
Freescale Semiconductor MPC5606S Data Sheet, Rev. 6 51
1 2 3 4 5 6 7
I/O Pad RESET direction type4 config.5 I/O M1 None, None
144 LQFP --
176 LQFP 42
208 MAPBG A D11
PK[8] PCR[129] Option 0 Option 1 Option 2 Option 3 PK[9] PCR[130] Option 0 Option 1 Option 2 Option 3 PK[10] PCR[131] Option 0 Option 1 Option 2 Option 3 PK[11] PCR[132] Option 0 Option 1 Option 2 Option 3 PK[12] PK[13] PK[14] PK[15] -- -- -- -- -- -- -- --
GPIO[129] MDO2 PDI[16] -- GPIO[130] MDO3 PDI[17] -- GPIO[131] SDA_1 eMIOSA[15] -- GPIO[132] SCL_1 eMIOSA[14] -- Reserved Reserved Reserved Reserved
SIUL Nexus PDI -- SIUL Nexus PDI -- SIUL I2C_1 PWM/Timer -- SIUL I2C_1 PWM/Timer -- -- -- -- --
--
I/O
M1
None, None
--
44
A10
--
I/O
S
None, None
--
52
N6
--
I/O
S
None, None
--
53
N5
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
Alternate functions are chosen by setting the values of the PCR[n].PA bitfields inside the SIUL module. PCR[n].PA = 00 -> Option 0; PCR[n].PA = 01 -> Option 1; PCR[n].PA = 10 -> Option 2; PCR[n].PA = 11-> Option 3. This is intended to select the output functions; to use one of the input functions, the PCR[n].IBE bit must be written to `1', regardless of the values selected in the PCR[n].PA bitfields. For this reason, the value corresponding to an input only function is reported as "--". Special functions are enabled independently from the standard digital pin functions. Enabling standard I/O functions in the PCR registers may interfere with their functionality. ADC functions are enabled using the PCR[APC] bit; other functions are enabled by enabling the respective module. Using the PSMI registers in the System Integration Unit Lite (SIUL), different pads can be multiplexed to the same peripheral input. Please see the SIUL chapter of the MPC5606S Microcontroller Reference Manual for details. See Table 9. Reset configuration is given as I/O direction and pull, e.g., "Input, Pullup". This option on this pin has alternate functions that depend on whether the QuadSPI is in SPI mode or in serial flash mode (SFM). Out of reset pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO and TMS respectively). It is up to the user to configure pins PH[0:3] when needed.
8
This pin can be used for LCD supply pin VLCD. Refer to the voltage supply pin descriptions in the MPC5606S data sheet for details.
52 MPC5606S Data Sheet, Rev. 6 Freescale Semiconductor
Table 9. Pad type descriptions
Abbreviation1 F J M1 M2 Description Fast (with GPIO and digital alternate function) Slow pads with analog muxing (built for ADC channels) Medium (with GPIO and digital alternate function) Programmable medium/slow pad (programmed via the slew rate control in the PCR): Slew rate disabled: Slow driver configuration (AC/DC parameters same as for a slow pad) Slew rate enabled: Medium driver configuration (AC/DC parameters same as for a medium pad) Slow (with GPIO and digital alternate function) Stepper motor driver (with slew rate control) Oscillator
S SMD X
1
The pad descriptions refer to the different Pad Configuration Register (PCR) types. Refer to the SIUL chapter in the device reference manual for the features available for each pad type.
2.9.1
Signal details
Table 10. Signal details
Signal Peripheral BAM ADC ADC Description Alternate Boot Select. Gives an option to boot by downloading code via CAN or LIN. Inputs used to bring into the device sensor-based signals for A/D conversion. ANS[0:15] connect to ATD channels [32:47]. These three control bits are output to enable the selection for an external Analog Mux for expansion channels. The available 8 multiplexed channels connect to ATD channels [64:71]. Force Alternate Boot mode. Forces the device to boot from the external bus (Can or LIN). If not asserted, the device boots up from the lowest flash sector containing a valid boot signature. DCU DCU DCU DCU Indicates that valid pixels are present. Horizontal sync pulse for TFT-LCD display Output pixel clock for TFT-LCD display Red, green and blue color 8-bit Pixel values for TFT-LCD displays
ABS[0] ANS[0:15] MA[0:2]
FABM
DCU_DE DCU_HSYNC DCU_PCLK DCU_R[0:7], DCU_G[0:7], DCU_B[0:7] DCU_TAG DCU_VSYNC PCS[0..2]_0, PCS[0..2]_1 SCK_0, SCK_1 SIN_0, SIN_1 SOUT_0, SOUT_1 PCS0_2 IO2/PCS1_2 IO3/PCS2_2 IO0/SIN_2 IO1/SOUT_2 SCK_2 eMIOSA[8:23], eMIOSB[16:23]
DCU DCU DSPI DSPI DSPI DSPI QuadSPI QuadSPI QuadSPI QuadSPI QuadSPI QuadSPI eMIOS
Indicates when a tagged pixel is present in safety mode Vertical sync pulse for TFT-LCD display Peripheral chip selects when device is in Master mode; not used in slave modes. SPI clock signal--bidirectional SPI data input signal SPI data output signal Peripheral chip select for serial flash mode or chip select 0 for SPI master mode Chip select 1 for SPI master mode and bidirectional IO2 for serial flash mode Chip select 2 for SPI master mode and bidirectional IO3 for serial flash mode Data input signal for SPI master and slave modes and bidirectional IO0 for serial flash mode Data output signal for SPI master and slave modes and bidirectional IO1 for serial flash mode Clock output signal for SPI master and serial flash modes and clock input signal for SPI slave mode Enhanced Modular Input Output System. 16+8 channel eMIOS for timed input or output functions.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 53
Table 10. Signal details (continued)
Signal CANRX_0, CANRX_1 Peripheral FlexCAN Description Receive (RX) pins for the CAN bus transceiver Transmit (TX) pins for the CAN bus transceiver Bidirectional serial clock compatible with I2C specifications
CANTX_0, CANTX_1 FlexCAN SCL_0, SCL_1, SCL_2, SCL_3 SDA_0, SDA_1, SDA_2, SDA_3 TCK TDI TDO TMS IC
2
I2C
Bidirectional serial data compatible with I2C specifications
JTAG JTAG JTAG JTAG
Debug port serial clock as per JTAG specifications Debug port serial data input port as per JTAG standards specifications Debug port serial data output port as per JTAG standards specifications Debug port Test Mode Select signal for the JTAG TAP controller state machine and indicates various state transitions for the TAP controller in the device Backplane signals from the LCD controlling the backplane reference voltage for the LCD display Frontplane signals for LCD segments Nexus2+ event input trigger Nexus2+ event output trigger Output clock for the development tool Message output port pins that send information bits to the development tools for messages such as Branch Trace Message (BTM), Ownership Trace Message (OTM), Data Trace Message (DTM). Only available in reduced port mode. Output pin--Indicates the start or end of the variable length message on the MDO pins Video/graphic data in various RGB modes input to the DCU Input signal indicates the validity of pixel data on the Input PDI data bus. Input indicates the timing reference for the start of each frame line for the PDI Input data. Input pixel clock from PDI Input indicates the timing reference for the start of a frame for the PDI input data. SCI/LIN Receive data signal--This port is used to download the code for the BAM boot sequence.
BP[0:3] FP[0:39] EVTI EVTO MCKO MDO[0:3]
LCD LCD Nexus Nexus Nexus Nexus
MSEO PDI[0:17] PDI_DE PDI_HSYNC PDI_PCLK PDI_VSYNC RXD_0
Nexus DCU (PDI) DCU (PDI) DCU (PDI) DCU (PDI) DCU (PDI) LINFlex
MPC5606S Microcontroller Data Sheet, Rev. 6 54 Freescale Semiconductor
Table 10. Signal details (continued)
Signal RXD_1 TXD_0 TXD_1 SOUND SSD[0:5]_0 SSD[0:5]_1 SSD[0:5]_2 SSD[0:5]_3 M[0:5]C0M M[0:5]C0P M[0:5]C1M M[0:5]C1P CLKOUT Peripheral LINFlex LINFlex LINFlex SGL SSD Description SCI/LIN Receive data signal. Input pad for the LIN SCI module. Connects to the internal LIN second port. SCI/LIN Transmit data signal. This port is used to download the code for the BAM boot sequence. SCI/LIN Transmit data signal--Transmit (output) port for the second LIN module in the chip Sound signal to the speaker/buzzer Bidirectional control of stepper motors using stall detection module
SMC
Controls stepper motors in various configuration
MC_CGM
Output clock--It can be selected from several internal clocks of the device from the clock generation module.
3
3.1
Electrical characteristics
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by internal pull up and pull down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" for System Requirement is included in the Symbol column.
3.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 11 are used and the parameters are tagged accordingly in the tables where appropriate.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 55
Table 11. Parameter Classifications
Classification tag P C T Tag description Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled "C" in the parameter tables where appropriate.
3.3
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the Nonvolatile User Options (NVUSRO) register. For a detailed description of the NVUSRO register, please see the chip reference manual.
3.3.1
NVUSRO[PAD3V5V] field description
Table 12. PAD3V5V field description1
Value2 0 1
1 2
Table 12 shows how NVUSRO[PAD3V5V] controls the device configuration.
Description High voltage supply is 5.0 V High voltage supply is 3.3 V
See the device reference manual for more information on the NVUSRO register. Default manufacturing value before Flash initialization is `1' (3.3 V)
The DC electrical characteristics are dependent on the PAD3V5V bit value.
3.3.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 13. OSCILLATOR_MARGIN field description1
Value2 0 1
1 2
Table 12 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Description Low consumption configuration (4 MHz/8 MHz) High margin configuration (4 MHz/16 MHz)
See the device reference manual for more information on the NVUSRO register. Default manufacturing value before Flash initialization is `1'
The 4-16 MHz fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.
MPC5606S Microcontroller Data Sheet, Rev. 6 56 Freescale Semiconductor
3.4
Absolute maximum ratings
Table 14. Absolute maximum ratings
Value Symbol VDDA VSSA VDDPLL VSSPLL VDDR VSSR VDD12 VSS12 VDDE_A
1
C
Parameter
Conditions Min Max 6.0 VSS + 0.1 1.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.3 VSS 0.1 -0.1
Unit V V V V V V V V V V V V V V V V V V
3
SR C Voltage on VDDA pin (ADC reference) with respect to ground (VSSA) SR C Voltage on VSSA (ADC reference) pin with respect to VSS CC C Voltage on VDDPLL (1.2 V PLL supply) pin with respect to ground (VSSPLL) SR C Voltage on VSSPLL pin with respect to VSS12 SR C Voltage on VDDR pin (regulator supply) with respect to ground (VSSR) SR C Voltage on VSSR (regulator ground) pin with respect to VSS CC C Voltage on VDD12 pin with respect to ground (VSS12) CC C Voltage on VSS12 pin with respect to VSS SR C Voltage on VDDE_A (I/O supply) pin with respect to ground (VSSE_A) SR C Voltage on VDDE_B (I/O supply) pin with respect to ground (VSSE_B) SR C Voltage on VDDE_C (I/O supply) pin with respect to ground (VSSE_C) SR C Voltage on VDDE_E (I/O supply) pin with respect to ground (VSSE_E) SR C Voltage on VDDMA (stepper motor supply) pin with respect to ground (VSSMA) SR C Voltage on VDDMB/C (stepper motor supply) pin with respect to ground (VSSMB) SR C I/O supply ground SR C Voltage on VSSOSC (oscillator ground) pin with respect to VSS SR C Voltage on VLCD (LCD supply) pin with respect to VSS
VSS12 0.1 VSS12 + 0.1 0.3 VSS 0.1 -0.1 VSS 0.1 0.3 0.3 0.3 0.3 0.3 0.3 0 VSS 0.1 0 0.3 0.3 6.0 VSS + 0.1 1.4 VSS + 0.1 6.0 6.0 6.0 6.0 6.0 6.0 0 VSS + 0.1 VDDE_A + 0.3 6.0 VDD + 0.3
VDDE_B1 VDDE_C1 VDDE_E1 VDDMA1 VDDMB1 VDDMC1 VSS2 VSSOSC VLCD VIN
SR C Voltage on any GPIO pin with respect to ground -- (VSS) C Relative to VDD
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 57
Table 14. Absolute maximum ratings (continued)
Value Symbol IINJPAD IINJSUM IMAX
1
C
Parameter
Conditions Min Max 10 50 45 150 -- -- -- -- 10 50 -- 55
Unit mA
SR C Injected input current on any pin during overload condition SR C Absolute sum of all injected input currents during overload condition CC D Absolute maximum current drive rating
TSTORAGE SR C Storage temperature
C
Throughout the remainder of this document VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC, unless otherwise noted. 2 Throughout the remainder of this document VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC, unless otherwise noted. 3 As long as the current injection specification is adhered to, then a higher potential is allowed.
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values.
MPC5606S Microcontroller Data Sheet, Rev. 6 58 Freescale Semiconductor
3.4.1
Recommended operating conditions
NOTE
Maximum slew time for the supplies to ramp up should be 1 second, which is slowest ramp-up time.
CAUTION
VDDE_C and VDDA must be the same voltage. VDDMB and VDDMC must be the same voltage. Table 15. Recommended operating conditions (3.3 V)
Value Symbol VDDA1 C Parameter Conditions Min SR C Voltage on VDDA pin (ADC reference) with respect to ground (VSS) C SR C Voltage on VSSA (ADC reference) pin with respect to VSS -- Relative to VDDE_C -- -- -- -- -- -- 3.0 VDD 0.1 VSS 0.1 0 3.0 0 VSS 0.1 3.0 Max 3.6 VDD + 0.1 VSS + 0.1 0 3.6 0 VSS + 0.1 3.6 V V V V V V V Unit
VSSA
VSSPLL SR C Voltage on VSSPLL pin with respect to VSS12 VDDR2 VSSR VSS124 VDD3,4,5 SR C Voltage on VDDR pin (regulator supply) with respect to ground (VSSR) SR C Voltage on VSSR (regulator ground) pin with respect to VSS12 CC C Voltage on VSS12 pin with respect to VSS SR C Voltage on VDD pins (VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB, VDDMC) with respect to ground (VSS) SR C I/O supply ground
VSS6
-- -- -- -- -- -- -- -- --
0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 0
0 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0
V V V V V V V V V
VDDE_A SR C Voltage on VDDE_A (I/O supply) pin with respect to ground (VSSE_A) VDDE_B SR C Voltage on VDDE_B (I/O supply) pin with respect to ground (VSSE_B) VDDE_C SR C Voltage on VDDE_C (I/O supply) pin with respect to ground (VSSE_C) VDDE_E SR C Voltage on VDDE_E (I/O supply) pin with respect to ground (VSSE_E) VDDMA VDDMB VDDMC SR C Voltage on VDDMA (stepper motor supply) pin with respect to ground (VSSMA) SR C Voltage on VDDMB (stepper motor supply) pin with respect to ground (VSSMB) SR C Voltage on VDDMC (stepper motor supply) pin with respect to ground (VSSMC)
VSSOSC SR C Voltage on VSSOSC (oscillator ground) pin with respect to VSS
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 59
Table 15. Recommended operating conditions (3.3 V) (continued)
Value Symbol VLCD TVDD TA TJ
1 2 3 4 5
C
Parameter
Conditions Min Max VDDE_A + 0.3 0.25 105 150 -- -- -- 0 510-6 40 40
Unit V V/s C
SR C Voltage on VLCD (LCD supply) pin with respect to VSS SR C VDD slope to ensure correct power up SR C Ambient temperature under bias SR C Junction temperature under bias
6
100 nF capacitance needs to be provided between VDDA/VSSA pair. At least 10 F capacitance must be connected between VDDR and VSS. This is required because of sharp surge due to external ballast. VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC. 100 nF capacitance needs to be provided between each VDD/VSS pair Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/O's DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL device is reset. VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC) unless otherwise noted.
Table 16. Recommended operating conditions (5.0 V)
Value Symbol VDDA1 C Parameter Conditions Min SR C Voltage on VDDA pin (ADC reference) with -- respect to ground (VSS) C Voltage drop2 C VSSA SR C Voltage on VSSA (ADC reference) pin with respect VSS Relative to VDDE_C -- -- 4.5 3.0 VDD 0.1 VSS 0.1 0 4.5 3.0 VDD 0.1 0 VSS 0.1 4.5 Max 5.5 5.5 VDD + 0.1 VSS + 0.1 0 5.5 5.5 VDD + 0.1 0 VSS + 0.1 5.5 V V V V V V V Unit
VSSPLL SR C Voltage on VSSPLL pin with respect to VSS12 VDDR3
-- SR C Voltage on VDDR pin (regulator supply) with respect to ground (VSSR) C Voltage drop2 C Relative to VDD -- -- Voltage drop2
VSSR VSS12 VDD4,5
SR C Voltage on VSSR (regulator ground) pin with respect to VSS12 CC C Voltage on VSS12 pin with respect to VSS SR C Voltage on VDD pins (VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB, VDDMC) with respect to ground (VSS) SR C I/O supply ground
VSS6
-- --
0 4.5
0 5.5
V V
VDDE_A SR C Voltage on VDDE_A (I/O supply) pin with respect to ground (VSSE_A)
MPC5606S Microcontroller Data Sheet, Rev. 6 60 Freescale Semiconductor
Table 16. Recommended operating conditions (5.0 V) (continued)
Value Symbol C Parameter Conditions Min VDDE_B SR C Voltage on VDDE_B (I/O supply) pin with respect to ground (VSSE_B) VDDE_C7 SR C Voltage on VDDE_C (I/O supply) pin with respect to ground (VSSE_C) VDDE_E SR C Voltage on VDDE_E (I/O supply) pin with respect to ground (VSSE_E) VDDMA VDDMB SR C Voltage on VDDMA (stepper motor supply) pin with respect to ground (VSSMA) SR C Voltage on VDDMB (stepper motor supply) pin with respect to ground (VSSMB) -- -- -- -- -- -- -- -- -- -- -- 4.5 4.5 4.5 4.5 4.5 4.5 0 0 310-6 40 40 Max 5.5 5.5 5.5 5.5 5.5 5.5 0 VDDE_A + 0.3 0.25 105 150 V V V V V V V V V/s C C Unit
VDDMC SR C Voltage on VDDMC (stepper motor supply) pin with respect to ground (VSSMC) VSSOSC SR C Voltage on VSSOSC (oscillator ground) pin with respect to VSS VLCD TVDD TA TJ
1 2 3 4 5 6 7
SR C Voltage on VLCD (LCD supply) pin with respect to VSS SR C VDD slope to ensure correct power up SR C Ambient temperature under bias SR C Junction temperature under bias
100 nF capacitance needs to be provided between VDDA/VSSA pair. Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical characteristics may not be guaranteed below 4.5 V during the voltage drop sequence. 10 F capacitance must be connected between VDDR and VSS12. This is required because of sharp surge due to external ballast. VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC. 100 nF capacitance needs to be provided between each VDD/VSS pair VSS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC) unless otherwise noted. VDDE_C should be the same as VDDA with a 100 mV variation, i.e., VDDE_C = VDDA 100 mV.
3.4.2
*
Connecting power supply pins: What to do and what not to do
Do: -- Have all power/ground supplies connected on the board from a strong supply source rather than weak voltage divider sources unless there is "NO IO activity" in the section -- Meet the supply specifications for max / typical operating conditions to guarantee correct operation -- Place the decoupling near the supply/ground pin pair for EMI emissions reduction -- Route high-noise supply/ground away from sensitive signals (for example, ADC channels must be away from SMD supply/motor pads) -- Use star routing for the ballast supply from the VDDR supply to avoid ballast startup noise injected to VDDR supply of the device -- Use LC inductive filtering for ADC, OSC, and PLL supplies if these are generated from common board regulators
MPC5606S Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
61
*
Do not: -- Violate injection current limit per IO/All IO pins as per specifications -- Connect sensitive supplies/ground on noisy supplies/ground (that is, ADC, PLL, and OSC) -- Use SMD supply for generation of noise free supply as these are most noisy lines in the system -- Connect different VDD pins (connected together inside the device) to different potentials.
3.5
Thermal characteristics
Table 17. LQFP thermal characteristics
Value Symbol RJA C Parameter Conditions 144-pin 176-pin CC D Thermal resistance, junction-to-ambient natural convection1 CC Single layer board--1s Four layer board--2s2p 50 41 41 35 29 10 2 43 35 35 30 24 9 2 C/W C/W C/W C/W C/W C/W C/W Unit
RJMA
CC D Thermal resistance, junction-to-moving-air @ 200 ft./min., single layer ambient2 board--1s CC @ 200 ft./min., four layer board--2s2p -- -- --
RJB
CC D Thermal resistance, junction-to-board2
RJCtop CC D Thermal resistance, junction-to-case (top)3 JT CC D Junction-to-package top thermal characterization parameter, natural convection4
Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 2 Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 3 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 4 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
1
3.5.1
General notes for specifications at maximum junction temperature
TJ = TA + (RJA PD) Eqn. 1
An estimate of the chip junction temperature, TJ, can be obtained from Equation 1:
where: = ambient temperature for the package (C) TA RJA = junction to ambient thermal resistance (C/W) = power dissipation in the package (W) PD
MPC5606S Microcontroller Data Sheet, Rev. 6 62 Freescale Semiconductor
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: * * * * Construction of the application board (number of planes) Effective size of the board which cools the component Quality of the thermal and electrical connections to the planes Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: * * * One oz. (35 micron nominal thickness) internal planes Components are well separated Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using Equation 2: TJ = TB + (RJB PD) where: = board temperature for the package perimeter (C) TB RJB = junction-to-board thermal resistance (C/W) per JESD51-8S = power dissipation in the package (W) PD When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (C/W) RJC = junction to case thermal resistance (C/W) RCA = case to ambient thermal resistance (C/W) RJC s device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. Eqn. 3 Eqn. 2
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 63
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using Equation 4: TJ = TT + (JT x PD) where: TT JT PD = thermocouple temperature on top of the package (C) = thermal characterization parameter (C/W) = power dissipation in the package (W) Eqn. 4
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 USA (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org.
3.6
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
3.6.1
* * * *
EMC requirements on board
Place a 100 nF capacitor between each of the VDD12/VSS12 supply pairs and also between the VDDPLL/VSSPLL pair. The voltage regulator also requires stability capacitors for these supply pairs. Place a 10 F capacitor on VDDR. Isolate VDDR with ballast emitter to avoid voltage droop during STANDBY mode exit. Enable pad slew rate only as necessary to eliminate I/O noise: -- Enabling slew rate for SMD pads will reduce noise on motors. -- Disabling slew rate for non-SMD pads will reduce noise on non-SMD IOs. Enable PLL modulation ( 2%) for system clock. Place decoupling capacitors for all HV supplies close to the pins.
The following practices help minimize noise in applications.
* *
MPC5606S Microcontroller Data Sheet, Rev. 6 64 Freescale Semiconductor
3.6.2
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for his application. * Software recommendations The software flowchart must include the management of runaway conditions such as: -- Corrupted program counter -- Unexpected reset -- Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.
*
3.6.3
Electromagnetic interference (EMI)
Table 18. EMI testing specifications1
Value
Symbol -- -- -- -- --
C
Parameter
Conditions Min Typ Max 150 kHz - 30 MHz: RBW 9 kHz, step size 5 kHz 30 MHz - 1 GHz: RBW 120 kHz, step size 80 kHz 0.15 -- -- -- -- -- --
Unit -- 1000 MHz 64 1.28 5 33 30 25 -- -- -- -- -- -- C MHz V V dBV
SR T Scan range
SR T Operating frequency Crystal frequency 8 MHz SR T VDD12, VDDPLL operating voltages SR T VDD, VDDA operating voltages -- --
SR T Maximum amplitude No PLL frequency modulation 2% PLL frequency modulation
--
1
SR T Operating temperature
--
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03.
3.6.4
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
3.6.4.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 65
Table 19. ESD absolute maximum ratings1 2
Symbol C Ratings Conditions TA = 25 C conforming to AEC-Q100-002 TA = 25 C conforming to AEC-Q100-003 TA = 25 C conforming to AEC-Q100-011 Class H1C M2 C3A Max value 2000 200 500 750 (corners) Unit V
VESD(HBM) CC T Electrostatic discharge voltage (Human Body Model) VESD(MM) CC T Electrostatic discharge voltage (Machine Model) VESD(CDM) CC T Electrostatic discharge voltage (Charged Device Model)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
3.6.4.2
* *
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. Table 20. Latch-up results
Symbol LU CC C Parameter Conditions TA = 105 C conforming to JESD 78 Class II level A
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
T Static latch-up class
3.7
3.7.1
Power management electrical characteristics
Voltage regulator electrical characteristics
The internal high power or main regulator (HPREG) requires an external NPN ballast transistor (see Table 21 and Table 22) to be connected as shown in Figure 7 as well as an external capacitance (CREG) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 15 nH. For the MPC5606S microcontroller, 100 nF should be placed between each of the VDD12/VSS12 supply pairs and also between the VDDPLL/VSSPLL pair. These decoupling capacitors are in addition to the required stability capacitance. Additionally, 10 F should be placed between the VDDR pin and the adjacent VSS pin. VDDR = 3.0 V to 3.6 V / 4.5 V to 5.5 V, TA = 40 to 105 C, unless otherwise specified.
MPC5606S Microcontroller Data Sheet, Rev. 6 66 Freescale Semiconductor
VDDR
VRC_CTRL 20 k VDD12 Figure 7. External NPN ballast connections Table 21. Allowed ballast components
Part BCP68 BCX68 BC817 BCP56 Manufacturer ON, IFX, NXP, Fairchild, ST, etc. IFX ON, IFX, NXP, Fairchild, etc. ON, IFX, NXP, Fairchild, ST, etc. Recommended derivative BCP68 BCX68-10 BCX68-16 BC817Su BC817-25 BCP68-10 BCP68-16
Table 22. Ballast component parameters
Parameter Capacitance on VDDR Stability capacitance on VDD12 Decoupling capacitance on VDD12 Specification 10 F (minimum) Place close to NPN collector 40 F (minimum) Place close to NPN emitter 100 nF number of pins (minimum) Place on each VDD12/VSS12 pair and on the PLL supply/ground pair 20 k
Base resistor
The capacitor values listed in Table 22 include a de-rating factor of 40%, covering tolerance, temperature, and aging effects. These factors are taken into account to assure proper operation under worst-case conditions. X7R type materials are recommended for all capacitors, based on ESR characteristics. Large capacitors are for regulator stability and should be located near the external ballast transistor. The number of capacitors is not important -- only the overall capacitance value and the overall ESR value are important. Small capacitors are for power supply decoupling, although they do contribute to the overall capacitance values. They should be located close to the device pin.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 67
Table 23. Voltage regulator electrical characteristics
Value Symbol TJ IREG C Parameter Conditions Min SR C Junction temperature CC C Current consumption -- Reference included, @ 55 C No load @ Full load DC load current Pre-trimming sigma < 7 mV Post-trimming 4 capacitances of 10 F each ESR of external cap 1 bond wire R + 1 pad R -- CL = 10 F 4 40 -- Typ -- -- 2 11 -- -- 1.145 -- 0.05 0.2 0 -- -- -- -- 1.330 1.28 -- -- 200 -- 1.32 10 4 0.2 1 15 30 100 30 30 CL = 10 F 4 -- -- 10% to 90% of IL (max) in 100 ns 100 s mA V V F nH dB Max 150 C mA Unit
IL
CC C Output current capacity
VDD12 CC C Output voltage P SR C External decoupling/stability capacitor C C LBOND CC D Bonding Inductance for Bipolar Base Control pad CC D Power supply rejection D D D CC D Load current transient @ DC @ no load @ 200 kHz @ no load @ DC @ 200 mA @ 200 kHz @ 200 mA
tSU
1
CC C Start-up time after input supply stabilizes1
CL = 10 F 4
--
--
Time after the input supply to the voltage regulator has ramped up (VDDR).
Table 24. Low-power voltage regulator electrical characteristics
Value Symbol TJ IREG C Parameter Conditions Min SR C Junction temperature CC C Current consumption -- Reference included, @ 55 C No load @ Full load DC load current Pre-trimming sigma < 7 mV Post-trimming 40 -- -- 5 600 -- -- 1.14 -- 1.33 1.24 1.32 15 mA V Typ Max 150 C A Unit
IL
CC C Output current capacity1
VDD12 CC C Output voltage P
MPC5606S Microcontroller Data Sheet, Rev. 6 68 Freescale Semiconductor
Table 24. Low-power voltage regulator electrical characteristics (continued)
Value Symbol C Parameter Conditions Min SR C External decoupling/stability capacitor C C LBOND CC D Bonding Inductance for Bipolar Base Control pad CC D Power supply rejection D D D CC D Load current transient tSU
1
Unit Max 10 4 0.6 1 15 55 32 24 12 F ohm ohm nH dB
Typ -- -- -- -- --
4 capacitances of 10 F each ESR of external cap 1 bond wire R + 1 pad R -- CL = 10 F 4
10 4 0.1 0.2 0 --
@ DC @ no load any frequency @ no load @ DC @ max load any frequency @ max load
CL = 10 F 4 CL = 10 F 4
-- --
-- --
10% to 90% of IL in 10 s 700 s
CC C Start-up time after input supply stabilizes2
On this device, the ultra-low-power regulator is always enabled when the low-power regulator is enabled. Therefore, the total low-power current capacity is the sum of IL values for the two regulators. 2 Time after the input supply to the voltage regulator has ramped up (V DDR) and the voltage regulator has asserted the Power OK signal.
Table 25. Ultra-low-power voltage regulator electrical characteristics
Value Symbol TJ IREG C Parameter Conditions Min SR C Junction temperature CC C Current consumption -- Reference included, @ 55 C No load @ Full load DC load current Pre-trimming sigma < 7 mV Post-trimming 40 -- Typ -- -- 2 100 -- -- 1.14 -- 1.33 1.24 5 -- 1.32 mA V Max 150 C A Unit
IL
CC C Output current capacity
VDD12 CC C Output voltage (value @ IL = 0 @ 27 C)
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 69
Table 25. Ultra-low-power voltage regulator electrical characteristics (continued)
Value Symbol C Parameter @ DC @ no load any frequency @ no load @ DC @ max load any frequency @ max load -- -- Conditions Min CC D Power supply rejection D D D CC D Load current transient -- -- Typ Max 25 7 25 8 10 to 90 A in 70 s dB Unit
3.7.2
Voltage monitor electrical characteristics
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD12 voltage while device is supplied: * * * * * POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0 V 10% range LVDLVCOR monitors power domain No. 1 LVDLVBKP monitors power domain No. 0 Table 26. Low voltage monitor electrical characteristics
Symbol VPORH VLVDHV3H VLVDHV5H VLVDHV3L VLVDHV5L C Parameter Conditions1 Min CC P Power-on reset threshold CC P LVDHV3 low voltage detector high threshold CC P LVDHV5 low voltage detector high threshold CC P LVDHV3 low voltage detector low threshold CC P LVDHV5 low voltage detector low threshold -- -- -- -- -- TA = 25 C, after trimming 1.5 -- -- 2.6 3.8 -- 1.08 Value Unit Typ -- -- -- -- -- -- -- Max 2.6 2.9 4.4 -- -- 1.14 -- V
VLVDLVCORH CC P LVDLVCOR low voltage detector high threshold VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified
3.7.3
Low voltage domain power consumption
Table 27 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application.
MPC5606S Microcontroller Data Sheet, Rev. 6 70 Freescale Semiconductor
Table 27. DC electrical characteristics
Symbol IDDRUN2 IDDHALT IDDSTOP C Parameter -- -- 16 MHz fast internal RC oscillator off, HPVREG off 16 MHz fast internal RC oscillator off, HPVREG on IDDSTDBY CC C STANDBY mode current IDDSTDBY13 CC P STANDBY1 mode current See Table 28 25C 105C TJ = 150C IDDSTDBY2 CC P STANDBY2 mode current
4
Conditions1
Value TA Min Typ 130 4 250 5 2.5 7 Max 180 25 1800 20 6.5 25 mA mA A mA mA mA -- -- 25C 105C 25C 105C -- -- -- -- Unit
CC P RUN mode current CC P HALT mode current CC P STOP mode current
-- -- -- -- -- --
20 180 350 30 350 600
100 -- 1500 100 -- 2500
A A A A A A
-- 25C 105C
TJ = 150C
1 2
--
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C Value is for maximum peripherals turned on. May vary significantly based on different configurations, active peripherals, operating frequency, etc. 3 ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption,all possible modules switched off. 4 ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum consumption, all possible modules switched off.
Table 28. IDDSTDBY specification1
Temperature (TA,C) -40 0 25 55 85 105 1252 150
1 2 2
FIRC off, 8 KB RAM on 3.3 V 16 A 18 A 23 A 41 A 93 A 173 A 320 A 681 A 5.5 V 25 A 29 A 33 A 51 A 104 A 185 A 334 A 698 A
FIRC on, 8 KB RAM on 3.3 V 326 A 334 A 342 A 363 A 421 A 502 A 648 A 1005 A 5.5 V 340 A 347 A 355 A 377 A 435 A 517 A 667 A 1028 A
32 kHz SXOSC on, 8 KB RAM on 3.3 V 16 A 19 A 24 A 42 A 100 A 181 A 321 A 654 A 5.5 V 26 A 29 A 34 A 53 A 110 A 194 A 335 A 677 A
32 kHz SXOSC on, all RAM on 3.3 V 22 A 26 A 34 A 69 A 182 A 344 A 620 A 1270 A 5.5 V 32 A 37 A 45 A 80 A 195 A 358 A 638 A 1300 A
All current values are typical values. Values provided for reference only. The permitted temperature range of the chip is specified separately.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 71
3.7.4
Recommended power-up and power-down order
Figure 8 shows the recommended order for powering up the power supplies on this device. The 1.2 V regulator output starts after the device's internal POR (VDDREG HV) is deasserted at approximately 2.7 V on VDDREG.
2.7 V
VDDREG HV supply
VDDREG HV POR (internal)
VA
1.2 V regulator output Soft startup (approx. 200 s)
VB
VDD IO HV supply (3-5.5 V)
>= 200 s
Figure 8. Recommended order for powering up the power supplies
CAUTION
The voltages VA and VB in Figure 8 must always obey the relation VB VA - 0.7 V. Otherwise, currents from the 1.2 V supply to the 3.3 V supply may result. Figure 9 shows the recommended order for powering down the power supplies on this device. It is acceptable for the VDD IO HV supply to ramp down faster than the 1.2 V regulator output, even if the latter takes time to discharge the high 40 F capacitance. (The capacitor will ultimately discharge.)
MPC5606S Microcontroller Data Sheet, Rev. 6 72 Freescale Semiconductor
2.7 V > 1.5 V
VDDREG HV supply
VDDREG HV POR (internal)
1.2 V regulator output Soft startup (approx. 200 s)
Time to discharge 40 F Capacitance depends on load
VDD IO HV supply (3-5.5 V)
Figure 9. Recommended order for powering down the power supplies
CAUTION
The VDD IO HV supply must be disabled after the VDDREG HV supply voltage drops below 1.5 V. This is to ensure that the 1.2 V regulator shuts down before the 3.3 V regulator shuts down.
3.7.5
Power-up inrush current profile
Figure 10 shows the power up inrush current profile of the ballast transistor under the worst possible startup condition (fastest PVT and fastest power ramp time).
1.2 V supply
Base control
Current profile
3-5.5 V
Figure 10. Power-up inrush current profile
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 73
The HPREG has a "soft startup" profile which increases the supply in steps of approximately 50 mV in a series of approximately 25 steps. Therefore, the peak current is within 750 mA of the maximum current during startup. This eliminates any noise on the VDDR supply during startup and charging of NPN emitter stability capacitance of 40 F (minimum). Soft startup also occurs when waking up from standby mode to limit noise on the VDDR supply. In case VDDR is shared between the device and the ballast, it must be star routed on the board or isolated as much as possible to avoid any noise injected by the ballast. Soft startup will help to limit this noise but a VDDR capacitor close to the ballast pin is critical here. A minimum capacitance of 10 F is needed. Table 29 shows the typical and maximum startup currents. Table 29. Startup current
Value Symbol ISTART CC C T Startup current Parameter Typ 300 Max 800 mA Unit
3.7.6
HPREG load regulation characteristics
The HPREG exhibits a very strong load-regulation behavior (the transition from low- to high-current state is regulated quickly). This is illustrated in Figure 12, which shows a 10-150 mA jump over 10 ns. Under any case of load transition, the HPREG responds within 100 ns and stabilizes within 5 s. This helps improve the stability of the 1.2 V supply and settling time.
1.2 V supply
Base control
3 V input supply
Load
Figure 11. HPREG load regulation
3.8
3.8.1
* *
I/O pad electrical characteristics
I/O pad types
Slow pads -- These are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads -- These are provided in two types (M1 and M2) and provide transitions fast enough for the serial communication channels. M2 pads include slew rate control.
The device provides five main I/O pad types:
MPC5606S Microcontroller Data Sheet, Rev. 6 74 Freescale Semiconductor
* * *
Fast pads -- These provide maximum speed. There are used for improved NEXUS debugging capability. SMD pads -- These provide additional current capability to drive stepper motor loads. Digital I/O with analog (J) pad -- These provide input and output digital features and analog input for ADC.
M2 and Fast pads can disable slew rate to reduce electromagnetic emission, at the cost of reducing AC performance.
3.8.2
I/O input DC characteristics
Table 30 provides input DC electrical characteristics as described in Figure 12.
VIN VDD VIH VHYS VIL
PDI = `1' (GPDI register of SIU)
PDI = `0'
Figure 12. I/O input DC electrical characteristics definition Table 30. I/O input DC electrical characteristics
Symbol VIH VIL C Parameter Conditions1 Min SR P Input high level CMOS Schmitt trigger SR P Input low level CMOS Schmitt trigger -- -- -- -- TA = -40C TA = 25C C P RON
1 2
Value Unit Typ -- -- -- -- 2 2 12 70 -- Max VDD + 0.3 0.35VDD -- 1 -- -- 500 1000 1 A nA nA nA nA k V 0.65VDD 0.3 0.1VDD -1 -- -- -- -- --
VHYS CC D Input hysteresis CMOS Schmitt trigger ILKG CC P Input leakage current
TA = 105C TJ = 150C
CC D Resistance of the analog switch inside the J Supply range pad type2 3.3-5 V
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C. Applies to the J pad type only.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 75
3.8.3
* * * * *
I/O output DC characteristics
Table 31 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 32 provides output driver characteristics for I/O pads when in SLOW configuration. Table 33 provides output driver characteristics for I/O pads when in MEDIUM configuration (applies to both M1 and M2 type pads). Table 34 provides output driver characteristics for I/O pads when in FAST configuration. Table 35 provides SMD pad characteristics. Table 31. I/O pull-up/pull-down DC electrical characteristics 1
The following tables provide DC characteristics for bidirectional pads:
Symbol
C
Parameter
Conditions2 Min VIN = VIL, VDD = 5.0V 10% VIN = VIL, VDD = 3.3V 10% VIN = VIL, VDD = 5.0V 10% VIN = VIL, VDD = 3.3V 10% PAD3V5V = 0 PAD3V5V = 13 PAD3V5V = 1 PAD3V5V = 0 PAD3V5V = 1 PAD3V5V = 1 10 10 10 10 10 10
Value Unit Typ -- -- -- -- -- -- Max 150 250 150 150 250 150 A A
|IWPU| CC P Weak pull-up current absolute value C P |IWPD| CC P Weak pull-down current absolute value C P
1 2
The pull currents are dependent on the HVE settings. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. 3 The configuration PAD3V5 = 1 when V DD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 32. SLOW configuration output buffer electrical characteristics
Symbol C Parameter Conditions1 Min VOH CC P Output high level SLOW configuration D C Push Pull, IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) Push Pull, IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 12 0.8VDD Value Unit Typ -- Max -- V
0.8VDD
-- --
-- --
Push Pull, IOH = 1 mA, VDD 0.8 VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) Push Pull, IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 12 Push Pull, IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) --
VOL CC P Output low level SLOW configuration D C
--
0.1VDD
V
-- --
-- --
0.1VDD 0.5
MPC5606S Microcontroller Data Sheet, Rev. 6 76 Freescale Semiconductor
Table 32. SLOW configuration output buffer electrical characteristics (continued)
Symbol Ttr C Parameter Conditions1 Min CC T Output transition time output CL = 25 pF, pin3 VDD = 5.0 V 10%, PAD3V5V = 0 SLOW configuration T CL = 50 pF, VDD = 5.0 V 10%, PAD3V5V = 0 T T T T Itr50 CC D Current slew at CL = 50 pF SLOW configuration D
1 2
Value Unit Typ -- -- -- -- -- -- -- Max 50 100 125 40 50 75 2 mA/ns ns -- -- -- -- -- -- --
CL = 100 pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 50 pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, VDD = 3.3 V 10%, PAD3V5V = 1 recommended configuration at VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 1
--
--
7
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are configured in input or in high impedance state. 3 C calculation should include device and package capacitances (C L PKG < 5 pF).
Table 33. MEDIUM configuration output buffer electrical characteristics
Symbol C Parameter Conditions1 Min VOH CC P Output high level MEDIUM configuration D C Push Pull, IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) Push Pull, IOH = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 12 Push Pull, IOH = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) Push Pull, IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 12 Push Pull, IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) 0.8VDD Value Unit Typ -- Max -- V
0.8VDD VDD 0.8
-- --
-- --
VOL CC P Output low level MEDIUM configuration D C
--
--
0.1VDD
V
-- --
-- --
0.1VDD 0.5
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 77
Table 33. MEDIUM configuration output buffer electrical characteristics (continued)
Symbol Ttr C Parameter Conditions1 Min CC T Output transition time out- CL = 25 pF, put pin3 VDD = 5.0 V 10%, PAD3V5V = 0 MEDIUM configuration T CL = 50 pF, VDD = 5.0 V 10%, PAD3V5V = 0 T T T T CL = 100 pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 50 pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- -- -- -- -- -- Value Unit Typ -- -- -- -- -- -- -- Max 10 20 40 12 25 40 7 mA/ns ns
Itr50 CC D Current slew at CL = 50 pF recommended configuration at MEDIUM configuration VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 D
1 2
VDD = 5.0 V 10%, PAD3V5V = 1
--
--
16
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are configured in input or in high impedance state. 3 C includes device and package capacitance (C L PKG < 5 pF).
Table 34. FAST configuration output buffer electrical characteristics
Symbol VOH C Parameter Conditions1 Min CC P Output high level FAST configuration D C Push Pull, IOH = 14 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) Push Pull, IOH = 7 mA, VDD = 5.0 V 10%, PAD3V5V = 12 0.8VDD Value Unit Typ -- Max -- V
0.8VDD
--
-- --
Push Pull, IOH = 11 mA, VDD 0.8 -- VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) Push Pull, IOL = 14 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 7 mA, VDD = 5.0 V 10%, PAD3V5V = 12 Push Pull, IOL = 11 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- --
VOL
CC P Output low level FAST configuration D C
0.1VDD
V
-- --
-- --
0.1VDD 0.5
MPC5606S Microcontroller Data Sheet, Rev. 6 78 Freescale Semiconductor
Table 34. FAST configuration output buffer electrical characteristics (continued)
Symbol Ttr C Parameter Conditions1 Min CC T Output transition time output CL = 25 pF, pin3 VDD = 5.0 V 10%, PAD3V5V = 0 FAST configuration T CL = 50 pF, VDD = 5.0 V 10%, PAD3V5V = 0 T T T T Itr50 CC D Current slew at CL = 50 pF FAST configuration D D
1 2
Value Unit Typ -- -- -- -- -- -- -- -- -- Max 4 6 12 4 7 12 55 40 100 mA/ns ns -- -- -- -- -- -- -- -- --
CL = 100 pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 50 pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 (recommended configuration) VDD = 3.3 V 10%, PAD3V5V = 1 (recommended configuration) VDD = 5.0 V 10%, PAD3V5V = 1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are configured in input or in high impedance state. 3 C includes device and package capacitance (C L PKG < 5 pF).
Table 35. SMD pad electrical characteristics
Value Symbol VIL VIH VHYST VOL C Parameter -- -- -- IOL = 20 IOL = 30 VOH CC P High level output voltage mA1 mA2 mA1 Conditions Min CC P Low level input voltage CC P High level input voltage CC C Schmitt trigger hysteresis CC P Low level output voltage -0.4 0.65VDDM 0.1VDDM -- -- VDDM-0.32 VDDM-0.48 Typ -- -- -- -- -- -- -- Max 0.35VDDM VDDM+0.4 -- 0.32 0.48 -- -- V Unit
IOH = -20
IOH = -30 mA2
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 79
Table 35. SMD pad electrical characteristics (continued)
Value Symbol IPU C Parameter Conditions Min CC P Internal pull-up device current Vin=VIL Vin=VIH IPD CC P Internal pull-down device current Vin=VIL Vin=VIH IIN RDSONH RDSONL CC P Input leakage current CC C SMD pad driver active high impedance CC C SMD pad driver active low impedance -- IOH -30 mA IOL 30 mA2 IOH / IOL 30 mA2
2
Unit Typ -- -- -- -- -- -- -- -- Max -- -10 -- 130 1 16 16 90 mV A -130 -- 10 -- -1 -- -- --
VOMATCH CC P Output driver matching VOH / VOL
1 2
VDD = 5.0 V 10%, Tj = -40 to 150 C. VDD = 5.0 V 10%, Tj = -40 to 130 C.
3.8.4
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 36. Table 37 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 36. I/O supply segment
Supply segment Package 144 LQFP 176 LQFP
1 2 3 4 5 6
A1 pins 1-21 pins 113-144 pins 1-21 pins 143-176
B2 pins 22- 52 pins 22-68
C3,4 pins 53-72 pins 69-88
D5 pins 73-102 pins 89-118
E6 pins 103-112 pins 119-142
LCD pad segment containing pad supplies VDDE_A Miscellaneous pad segment containing pad supplies VDDE_B ADC pad segment containing pad supplies VDDE_C VDDE_C should be the same as VDDA with a 100 mV variation, i.e., VDDE_C = VDDA 100 mV. Stepper Motor pad segment containing I/O supplies VDDMA, VDDMB, VDDMC Miscellaneous pad segment containing pad supplies VDDE_E
MPC5606S Microcontroller Data Sheet, Rev. 6 80 Freescale Semiconductor
Table 37. I/O consumption
Symbol ISWTSLW C Parameter Conditions1 Min CC D Dynamic I/O current for SLOW configuration D ISWTMED CL = 25 pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Value Unit Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 20 16 29 17 110 50 2.3 3.2 6.6 1.6 2.3 4.7 6.6 13.4 18.3 5.0 8.5 11.0 mA mA mA mA mA
CC D Dynamic I/O current for MEDIUM CL = 25 pF, configuration VDD = 5.0 V 10%, PAD3V5V = 0 D CL = 25 pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 25 pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF, VDD = 3.3 V 10%, PAD3V5V = 1
ISWTFST
CC D Dynamic I/O current for FAST configuration D
IRMSSLW
CC D Root mean square I/O current for CL = 25 pF, 2 MHz SLOW configuration VDD = 5.0 V 10%, PAD3V5V = 0 D D D D D CL = 25 pF, 4 MHz VDD = 5.0 V 10%, PAD3V5V = 0 CL = 100 pF, 2 MHz VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF, 2 MHz VDD = 3.3 V 10%, PAD3V5V = 1 CL = 25 pF, 4 MHz VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz VDD = 3.3 V 10%, PAD3V5V = 1
IRMSMED
CC D Root mean square I/O current for CL = 25 pF, 2 MHz MEDIUM configuration VDD = 5.0 V 10%, PAD3V5V = 0 D D D D D CL = 25 pF, 4 MHz VDD = 5.0 V 10%, PAD3V5V = 0 CL = 100 pF, 2 MHz VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF, 2 MHz VDD = 3.3 V 10%, PAD3V5V = 1 CL = 25 pF, 4 MHz VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz VDD = 3.3 V 10%, PAD3V5V = 1
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 81
Table 37. I/O consumption (continued)
Symbol IRMSFST C Parameter Conditions1 Min CC D Root mean square I/O current for CL = 25 pF, 2 MHz FAST configuration VDD = 5.0 V 10%, PAD3V5V = 0 D D D D D IDYNSEG CL = 25 pF, 4 MHz VDD = 5.0 V 10%, PAD3V5V = 0 CL = 100 pF, 2 MHz VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF, 2 MHz VDD = 3.3 V 10%, PAD3V5V = 1 CL = 25 pF, 4 MHz VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz VDD = 3.3 V 10%, PAD3V5V = 1 -- -- -- -- -- -- -- -- -- -- -- -- Value Unit Typ -- -- -- -- -- -- -- -- -- -- -- -- Max 22.0 33.0 56.0 14.0 20.0 25.0 110 65 70 65 90 120 mA mA mA
SR D Sum of all the dynamic and static VDD = 5.0 V 10%, PAD3V5V = 0 I/O current within a supply segD VDD = 3.3 V 10%, PAD3V5V = 1 ment SR D Sum of all the static I/O current within a supply segment D VDD = 5.0 V 10%, PAD3V5V = 0 VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 TJ = 130 C VDD = 5.0 V 10%, PAD3V5V = 0 TJ = -40 C
IAVGSEG
IDDMxAVG SR D Sum of currents of two motors assigned to segment VDDMx, VSSMx pair
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified
3.9
3.9.1
SSD specifications
Electrical characteristics
Table 38. SSD electrical characteristics
Value Symbol VVREF IVREF RIN VIN SSDCONST C Parameter Min CC P Reference voltage (IVREF = 0) CC P Reference voltage output current CC D Input resistance (against VDDM/2) CC C Input common mode range CC C SSD constant VDDM/2 - 0.02 2.5 0.8 VSSM 0.549 Typ VDDM/2 -- 1.0 -- 0.572 Max VDDM/2 + 0.02 -- 1.2 VDDM 0.597 V mA M V -- Unit
MPC5606S Microcontroller Data Sheet, Rev. 6 82 Freescale Semiconductor
Table 38. SSD electrical characteristics (continued)
Value Symbol SSDOFFSET C Parameter Min CC C SSD offset (unipolar, Nsample = 256) SSD offset (bipolar, Nsample = 256) SSD offset (bipolar with offset cancellation, Nsample = 256) fSSDSMP CC D SSD cmpout sample rate -9 -8 -5 0.5 Typ -- -- -- -- Max 9 8 5 2.0 MHz counts Unit
3.9.2
Accumulator values
Equation 5 describes the accumulator value in unipolar configuration. The voltage Vin is applied between the integrator input and VDDM. The internal generated reference voltage is not connected. The accumulator value is a function of VDDM, the number of samples (Nsample) taken and the SSD constant (SSDconst). The SSD constant and offset (SSDconst, SSDoffset) vary with temperature and process.
V in - VDDM 2 ACCval = ----------------------------------------------- Nsample + SSDoffset VDDM SSDconst
Eqn. 5 Equation 6 describes the accumulator value in bipolar configuration. The voltage Vin is applied between the integrator input and the reference output. The accumulator value depends on the same parameters as in the unipolar case but the inaccuracy of the voltage reference (Vvref) is compensated.
V in ACCval = ----------------------------------------------- Nsample + SSDoffset VDDM SSDconst
Eqn. 6
3.10
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 83
Figure 13. Start-up reset requirements
VDD VDDMIN
RESET
VIH VIL device reset forced by RESET device start-up phase
Figure 14. Noise filtering on reset signal
VRESET hw_rst
VDD
`1'
VIH
VIL
`0'
filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset
MPC5606S Microcontroller Data Sheet, Rev. 6 84 Freescale Semiconductor
Table 39. Reset electrical characteristics
Symbol VIH VIL VHYS VOL C Parameter -- Conditions1 Min SR P Input high level CMOS Schmitt Trigger 0.65VDD 0.4 0.1VDD -- Value Unit Typ -- -- -- -- Max VDD + 0.4 0.35VDD -- 0.1VDD V V V V
SR P Input low level CMOS Schmitt -- Trigger CC D Input hysteresis CMOS Schmitt Trigger CC P Output low level -- Push Pull, IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 12 Push Pull, IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) CL = 25 pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 50 pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 100 pF, VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 50 pF, VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, VDD = 3.3 V 10%, PAD3V5V = 1 --
D C
-- --
-- --
0.1VDD 0.5
Ttr
CC T Output transition time output pin3 MEDIUM configuration T T T T T
-- -- -- -- -- -- -- 1000 10 -- --
-- -- -- -- -- -- -- -- -- 10 20
10 20 40 12 25 40 40 -- 150 -- --
ns
WFRST SR P RESET input filtered pulse
ns ns A mA mA
WNFRST SR P RESET input not filtered pulse -- IWPU CC P Weak pull-up current absolute -- value D RUN Current during RESET Before Flash is ready After Flash is ready
1 2
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to reset generation module (RGM) section of the device reference manual). 3 C includes device and package capacitance (C L PKG < 5 pF).
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 85
3.11
Fast external crystal oscillator (4-16 MHz) electrical characteristics
The device provides an oscillator/resonator driver. Figure 15 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator.
XTAL CL Crystal EXTAL XTAL
DEVICE
VDD
CL
I
R
XTAL EXTAL Resonator EXTAL
DEVICE
DEVICE
Figure 15. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits. Table 40. Crystal description
Crystal equivalent series resistance ESR 300 300 150 120 120 Crystal motional capacitance (Cm) fF 2.68 2.46 2.93 3.11 3.90 Crystal motional inductance (Lm) mH 591.0 160.7 86.6 56.5 25.3 Load on xtalin/xtalout C1 = C2 (pF)1 21 17 15 15 10 Shunt capacitance between xtalout and xtalin C02 (pF) 2.93 3.01 2.91 2.93 3.00
Nominal frequency (MHz)
NDK crystal reference
4 8 10 12 16
NX8045GB NX5032GA
MPC5606S Microcontroller Data Sheet, Rev. 6 86 Freescale Semiconductor
1
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.).
Table 41. Resonator description
CSTCR4M00G53-R0 Vibration Fr (kHz) Fa (kHz) Fa-Fr (dF) (kHz) Ra (k) R1 () L1 (mH) C1 (pF) Co (pF) Qm CL1 (nominal) (pF) CL2 (nominal) (pF) 3929.50 4163.25 233.75 372.41 12.78 0.84443 1.94268 15.85730 1630.93 15 15 CSTCR4M00G55-R0
Fundamental 3898.00 4123.00 225.00 465.03 11.38 0.88244 1.88917 15.90537 1899.77 39 39
S_MTRANS bit (ME_GS register) `1'
`0' VXTAL VFXOSC VFXOSCOP 10% tFXOSCSU valid internal clock
1/fFXOSC 90%
Figure 16. Fast external crystal oscillator (4-16 MHz) electrical characteristics
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 87
Table 42. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol fFXOSC gmFXOSC C Parameter Conditions1 Min SR -- Fast external crystal oscillator frequency CC C Fast external crystal oscillator transconductance CC P -- VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 0 VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 1 VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 VFXOSCOP CC C Oscillation operating point IFXOSC,2 TFXOSCSU CC T Fast external crystal oscillator consumption CC T Fast external crystal oscillator start-up time -- -- fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 VIH VIL
1 2
Value Unit Typ -- -- Max 16.0 8.2 MHz mA/V 4.0 2.2
2.0
--
7.4
CC C
2.7
--
9.7
CC C
2.5
--
9.2
VFXOSC
CC T Oscillation amplitude at EXTAL
1.3 1.3 -- -- -- -- 0.65VDD 0.4
-- -- 0.95 2 -- -- -- --
-- -- -- 3 6 1.8 VDD+0.4 0.35VDD
V
V mA ms
SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger)
Oscillator bypass mode Oscillator bypass mode
V V
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals)
3.12
Slow external crystal oscillator (32 KHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
MPC5606S Microcontroller Data Sheet, Rev. 6 88 Freescale Semiconductor
PC[15] CX
PC[15] Resonator PC[14] CY
PC[14]
DEVICE
Crystal
DEVICE
Figure 17. Crystal oscillator and resonator connection scheme
NOTE
PC[14]/PC[15] must not be directly used to drive external circuits.
OSCON bit (OSC_CTL register) `1'
`0'
VSXOSC_XTAL VSXOSC 90%
1/fSXOSC
10% TSXOSCSU valid internal clock
Figure 18. Slow external crystal oscillator (32 KHz) timing
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 89
Table 43. Slow external crystal oscillator (32 KHz) electrical characteristics
Symbol fSXOSC VSXOSC C Parameter Conditions1 Min SR T Slow external crystal oscillator -- frequency CC T Oscillation amplitude T ISXOSC VDD = 3.3 V 10% VDD = 5.0 V 10% 32 1.12 1.12 -- -- 0.65VDD 0.4 Value Unit Typ -- 1.33 1.37 -- -- -- -- Max 40 1.74 1.74 5 22 VDD + 0.4 0.35VDD A s V V kHz V
CC D Slow external crystal oscillator -- consumption
TSXOSCSU CC T Slow external crystal oscillator -- start-up time VIH VIL
1 2
SR D Input high level CMOS Schmitt Oscillator bypass mode Trigger SR D Input low level CMOS Schmitt Oscillator bypass mode Trigger
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified The quoted figure is based on a board that is properly laid out and has no stray capacitances.
3.13
FMPLL electrical characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Table 44. FMPLL electrical characteristics
Symbol fPLLIN PLLIN C Parameter -- cycle2 -- -- -- Stable oscillator (fPLLIN = 16 MHz) fPLLIN = 16 MHz (resonator) fPLLIN = 16 MHz (resonator) TA = 25 C Conditions1 Min SR T FMPLL reference clock2 SR T FMPLL reference clock duty 4 40 16 -- -- -- -- -- Value Unit Typ -- -- -- -- -- -- -- -- Max 64 60 64 643 200 220 1.5 4 MHz % MHz MHz s ps ns mA
fPLLOUT CC T FMPLL output clock frequency fCPU tLOCK CC T System clock frequency CC T FMPLL lock time
tPKJIT CC T FMPLL jitter (peak to peak) tLTJIT CC T FMPLL long term jitter IPLL
1 2
CC D FMPLL consumption
VDDPLL = 1.2 V 10%, TA = 40 to 105 C, unless otherwise specified. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 3f CPU 64 MHz can be achieved only at temperatures up to TA = 105 C with a maximum FM depth of 2%.
MPC5606S Microcontroller Data Sheet, Rev. 6 90 Freescale Semiconductor
3.14
Fast internal RC oscillator (16 MHz) electrical characteristics
Table 45. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol fFIRC C Parameter Conditions1 Value Unit Min Typ Max CC P Fast internal RC oscillator high TA = 25 C, trimmed frequency SR -- -- Trimmed -- 16 12 5 -- 20 +5 % MHz
The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device.
FIRCVAR CC C Fast internal RC oscillator variation across temperature (TA = -40C to 105C) and supply with respect to fFIRC at TA = 25 C in high-frequency configuration
IFIRCRUN CC D Fast internal RC oscillator high TA = 25 C, trimmed -- frequency current in running mode IFIRCPWD CC D Fast internal RC oscillator high TA = 25 C frequency current in power down mode IFIRCSTOP CC D Fast internal RC oscillator high TA = 25 C frequency and system clock D current in stop mode D D D tFIRCSU
1
--
--
200
A
--
--
--
1
A
sysclk = off sysclk = 2 MHz sysclk = 4 MHz sysclk = 8 MHz sysclk = 16 MHz VDD = 5.0 V 10%
-- -- -- -- -- --
0.3 2 2.5 3.3 5.2 1
-- -- -- -- -- 2
mA
CC P Fast internal RC oscillator start-up time
s
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified.
3.15
Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 91
Table 46. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol fSIRC C Parameter Conditions1 Min CC P Slow internal RC oscillator low frequency SR -- TA = 25 C, trimmed -- -- 100 -10% Value Unit Typ 128 Max -- 150 +10% kHz kHz
SIRCVAR CC C Slow internal RC oscillator variation Trimmed across temperature (TA = -40C to 105C) and supply with respect to fSIRC at TA = 25 C in high frequency configuration ISIRC tSIRCSU
1
CC D Slow internal RC oscillator low frequency current
TA = 25 C, trimmed
-- --
-- 8
5 12
A s
CC C Slow internal RC oscillator start-up time TA = 25 C, VDD = 5.0 V 10%
VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified.
3.16
Flash memory electrical characteristics
Table 47. Program and erase specifications
Value Symbol C Parameter Typ1 22 300 400 800 -- Initial max2 50 500 600 1300 30 Max3 500 5000 5000 7500 30 Unit
Tdwprogram T16kpperase T32kpperase T128kpperase Teslat
1 2
CC C Double word (64 bits) program time4 CC C 16 KB block pre-program and erase time CC C 32 KB block pre-program and erase time CC C 128 KB block pre-program and erase time CC D Erase suspend latency
s ms ms ms s
Typical program and erase times assume nominal supply values and operation at 25 C. Initial factory condition: < 100 program/erase cycles, 25 C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead.
MPC5606S Microcontroller Data Sheet, Rev. 6 92 Freescale Semiconductor
Table 48. Flash module life
Value Symbol P/E C Parameter Conditions Min CC C Number of program/erase cycles per block for 16 KB blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 32 KB blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 128 KB blocks over the operating temperature range (TJ) -- 100000 Typ -- cycles Unit
P/E
--
10000
100000 cycles
P/E
--
1000
100000 cycles
Retention CC C Minimum data retention at 85 C average ambient temperature1
Blocks with 0-1,000 P/E cycles Blocks with 10,000 P/E cycles Blocks with 100,000 P/E cycles
20 10 5
-- -- --
years years years
1
Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range.
Table 49. Flash memory read access timing
Symbol fREAD C Parameter Condition1 2 wait states 1 wait state 0 wait states Max value 64 40 20 Unit MHz
CC P Maximum frequency for flash memory reading C C
1
VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 105 C, unless otherwise specified
3.17
ADC electrical characteristics
The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 93
Offset Error OSE 1023
Gain Error GE
1022 1021
1020 1019 1 LSB ideal = VDDA / 1024 1018 (2)
code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve
2 1
1 LSB (ideal)
0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal)
Offset Error OSE
Figure 19. ADC Characteristics and Error Definitions
3.17.1
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.
MPC5606S Microcontroller Data Sheet, Rev. 6 94 Freescale Semiconductor
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 7: Eqn. 7 R S + R F + R L + R SW + R AD -1 V A -------------------------------------------------------------------------- -- LSB R EQ 2 Equation 7 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1
Sampling
Source RS
Filter RF
Current Limiter RL
RAD
VA
CF
CP1
CP2
CS
RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance
Figure 20. Input equivalent circuit (precise channels)
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 95
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Extended Switch RSW2
Sampling
Source RS
Filter RF
Current Limiter RL
RAD
VA
CF
CP1
CP3
CP2
CS
RS RF CF RL RSW RAD CP CS
Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance
Figure 21. Input equivalent circuit (extended channels) A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 20): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close).
VCS VA VA2
Voltage transient on CS V <0.5 LSB
1 2
1 < (RSW + RAD) CS << TS
VA1
2 = RL (CS + CP1 + CP2)
TS t
Figure 22. Transient behavior during sampling phase In particular two different transient periods can be distinguished: * A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is
MPC5606S Microcontroller Data Sheet, Rev. 6 96 Freescale Semiconductor
CP CS 1 = R SW + R AD -------------------CP + CS
Eqn. 8
Equation 8 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: Eqn. 9 1 R SW + R AD C S T S The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 10: Eqn. 10 V A1 C S + C P1 + C P2 = V A C P1 + C P2 * A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: Eqn. 11 2 R L C S + C P1 + C P2 In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: Eqn. 12 10 2 = 10 R L C S + C P1 + C P2 TS Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 13 must be respected (charge balance assuming now CS already charged at VA1): Eqn. 13 VA2 C S + C P1 + C P2 + C F = V A C F + V A1 C P1 + C P2 + C S The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 97
Analog source bandwidth (VA) Noise
TC 2 RFCF (conversion rate vs. filter pole) fF f0 (anti-aliasing filtering condition) 2 f0 fC (Nyquist)
f0
f
Sampled signal spectrum (fC = conversion rate)
Anti-aliasing filter (fF = RC filter pole)
fF
f
f0
fC
f
Figure 23. Spectral representation of input signal Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 14 between the ideal and real sampled voltage on CS: Eqn. 14 VA C P1 + C P2 + C F ----------- = ------------------------------------------------------V A2 C P1 + C P2 + C F + C S From this formula, in the worst case (when VA is maximum, that is for instance 5V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Eqn. 15 C F 2048 C S
3.17.2
ADC conversion characteristics
NOTE
For input leakage current specification, see Table 30.
MPC5606S Microcontroller Data Sheet, Rev. 6 98 Freescale Semiconductor
Table 50. ADC conversion characteristics
Symbol VSSA C Parameter Conditions1 Min SR D Voltage on VSSA (ADC -- reference) pin with respect to ground (VSS)2 SR D Voltage on VDDA pin (ADC reference) with respect to ground (VSS) SR D Analog input voltage3 SR D ADC analog frequency -- 0.1 Value Unit Typ -- Max 0.1 V
VDDA
VDD 0.1
--
VDD + 0.1
V
VAINx fADC
-- -- -- fADC = 32 MHz, ADC_conf_sample_input = 17 fADC = 6 MHz, ADC_conf_sample_input = 127 fADC = 32 MHz, ADC_conf_comp = 2 -- -- -- -- -- -- -- Current injection on one ADC input, different from the converted one No overload
VSSA 0.1 6 -- 0.5 -- 0.625 -- -- -- -- -- -- -- 5
-- -- -- -- -- -- -- -- -- -- -- -- -- --
VDDA + 0.1 32 1.5 -- 21 -- 3 3 1 1 1 1 0.1 5
V MHz s s
tADC_PU SR D ADC power up delay tADC_S CC T Sample
T
time4,5
tADC_C CS CP1 CP2 CP3 RSW1 RSW2 RAD IINJ
CC T Conversion time6 CC D ADC input sampling capacitance CC D ADC input pin capacitance 1 CC D ADC input pin capacitance 2 CC D ADC input pin capacitance 3 CC D Internal resistance of analog source CC D Internal resistance of analog source CC D Internal resistance of analog source SR T Input current Injection
s pF pF pF pF k k k mA
INL DNL OFS GNE TUEx
CC P Integral Non Linearity
.5 1.0 -- -- -3 -4
-- -- 0.5 0.6 -- --
2.5 1.0 -- -- 3 4
LSB LSB LSB LSB LSB
CC P Differential Non Linearity No overload CC T Offset error CC T Gain error CC P Total unadjusted error for Without current injection extended channel T With current injection After offset cancellation
1
VDDA = 3.3 V 10% / 5.0 V 10%, TA = 40 to 105 C, unless otherwise specified.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 99
2 3 4
5
6
Analog and digital VSS must be common (to be tied together externally). VAINx may exceed VSSA and VDDA limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming. The maximum sample rate is 1 million samples per second, provided the source impedance and current limiter(>1 k) are calculated adequately. Filter capacitor at analog source output must meet the criteria Cf (filter capacitor) > 2048*Cs (sampling capacitor which is 3 pF ) This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result's register with the conversion result.
3.18
LCD driver electrical characteristics
Table 51. LCD driver specifications
Value1 Symbol VLCD ZBP/FP C Parameter Min SR C Voltage on VLCD (LCD supply) pin with respect to VSS CC T LCD output impedance (BP[n-1:0],FP[m-1:0]) for output levels VLCD, VSS2 T LCD output current (BP[n-1:0],FP[m-1:0]) for outputs charge/discharge voltage levels VLCD2/3, VLCD1/2, VLCD1/3)2,3 0 -- Typ -- -- Max VDDE + 0.3 5.0 V k Unit
IBP/FP
CC
--
25
--
A
1 2
VDD = 5.0 V 10%, TA = -40-105 C, unless otherwise specified Outputs measured one at a time, low impedance voltage source connected to the VLCD pin. 3 With PWR=10, BSTEN=0, and BSTAO=0
3.19
Pad AC specifications
Table 52. Pad AC specifications (5.0 V, PAD3V5V = 0)1
Tswitchon1 (ns) Min 1 Slow 1.5 1.5 1.5 1.5 Typ -- -- -- -- Max 30 30 30 30 Rise/Fall2 (ns) Min 6 9 12 16 Typ -- -- -- -- Max 50 100 125 150 Frequency (MHz) Min -- -- -- -- Typ -- -- -- -- Max 4 2 2 2 Current slew (mA/ns) Min 0.04 0.04 0.04 0.04 Typ -- -- -- -- Max 2 2 2 2 25 50 100 200 Load drive (pF)
No.
Pad
MPC5606S Microcontroller Data Sheet, Rev. 6 100 Freescale Semiconductor
Table 52. Pad AC specifications (5.0 V, PAD3V5V = 0)1 (continued)
Tswitchon1 (ns) Min 2 Medium 1 1 1 1 3 Fast 1 1 1 1 4 Pull Up/Down (5.5 V max) Parameter Classification
1 2
No.
Pad
Rise/Fall2 (ns) Min 3 5 9 12 1 1.5 3 5 -- Typ -- -- -- -- -- -- -- -- -- Max 10 20 40 70 4 6 12 16 5000
Frequency (MHz) Min -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- Max 40 20 13 7 100 80 40 25 --
Current slew (mA/ns) Min 2.5 2.5 2.5 2.5 18 18 18 18 -- Typ -- -- -- -- -- -- -- -- -- Max 7 7 8 8 55 55 55 55 --
Load drive (pF) 25 50 100 200 25 50 100 200 50
Typ -- -- -- -- -- -- -- -- --
Max 15 15 15 15 6 6 6 6 --
--
D
C
C
C
n/a
Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition Slope at rising/falling edge
Table 53. Pad AC specifications (3.3 V, PAD3V5V = 1)1
Tswitchon1 (ns) Min 1 Slow 3 3 3 3 2 Medium 1 1 1 1 Typ -- -- -- -- -- -- -- -- Max 40 40 40 40 15 15 15 15 Rise/Fall2 (ns) Min 4 6 10 14 2 4 8 14 Typ -- -- -- -- -- -- -- -- Max 40 50 75 100 12 25 40 70 Frequency (MHz) Min -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- Max 4 2 2 2 40 20 13 7 Current slew (mA/ns) Min 0.01 0.01 0.01 0.01 2.5 2.5 2.5 2.5 Typ -- -- -- -- -- -- -- -- Max 2 2 2 2 7 7 7 7 25 50 100 200 25 50 100 200 Load drive (pF)
No.
Pad
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 101
Table 53. Pad AC specifications (3.3 V, PAD3V5V = 1)1 (continued)
Tswitchon1 (ns) Min 3 Fast 1 1 1 1 4 Pull Up/Down (3.6 V max) Parameter Classification
1 2
No.
Pad
Rise/Fall2 (ns) Min 1 1.5 3 5 -- Typ -- -- -- -- -- Max 4 7 12 18 7500
Frequency (MHz) Min -- -- -- -- -- Typ -- -- -- -- -- Max 72 55 40 25 --
Current slew (mA/ns) Min 3 3 3 3 -- Typ -- -- -- -- -- Max 40 40 40 40 --
Load drive (pF) 25 50 100 200 50
Typ -- -- -- -- --
Max 6 6 6 6 --
--
D
C
C
C
n/a
Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition Slope at rising/falling edge
VDD/2 Pad Data Input
Rising Edge Output Delay
Falling Edge Output Delay
VOH
Pad Output
VOL
Figure 24. Pad output delay
MPC5606S Microcontroller Data Sheet, Rev. 6 102 Freescale Semiconductor
Table 54. SMD pad delays
Value Symbol -- C Parameter Conditions Min CC D SMD pad delay CL=50pf VDD=5V10% SRE=1 CL=50pf VDD=5V10% SRE=0 -- CC D SMD pad delay CL=50pf VDD=3.3V10% SRE=1 CL=50pf VDD=3.3V10% SRE=0 -- Typ -- Max 165 ns Unit
--
--
35
--
--
350
--
--
50
3.20
3.20.1
AC timing
IEEE 1149.1 interface timing
Table 55. JTAG interface timing1
Value
No. 1 2 3 4 5 6 7 8
1
Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH tTDOV tTDOI tTDOHZ
C CC D TCK Cycle Time
Parameter Min 100 40 -- 5 10 -- 0 -- Max -- 60 3 -- -- 40 -- 30
Unit ns
CC D TCK Clock Pulse Width (measured at VDD/2) CC D TCK Rise and Fall Times (40%-70%) CC D TMS, TDI Data Setup Time CC D TMS, TDI Data Hold Time CC D TCK Low to TDO Data Valid CC D TCK Low to TDO Data Invalid CC D TCK Low to TDO High Impedance
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 3.0 V to 5.5 V, TA = 40 to 105 C, and CL = 50 pF with SRC = 0b11.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 103
TCK 2 3 2
1
3
Figure 25. JTAG test clock input timing
TCK
4 5
TMS, TDI
6 7 8
TDO
Figure 26. JTAG test access port timing
MPC5606S Microcontroller Data Sheet, Rev. 6 104 Freescale Semiconductor
TCK
9
11
Output Signals
10
Output Signals 12 13
Input Signals
Figure 27. JTAG boundary scan timing
3.20.2
Nexus debug interface
Table 56. Nexus debug port timing1
Value
No. 1 2 3 4 5 6 7
Symbol tMCYC MDC tMDOV tMSEOV tEVTOV tEVTIPW tEVTOPW CC CC CC CC CC CC CC
C
Parameter Min Max -- 60 14 14 14 -- -- 22 40
2
Unit ns % ns ns ns tTCYC tMCYC
D MCKO Cycle Time D MCKO Duty Cycle D MCKO Low to MDO Data Valid D MCKO Low to MSEO Data D MCKO Low to EVTO Data D EVTI Pulse Width D EVTO Pulse Width Valid2 Valid2
-2 -2 -2 4 1
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 105
Table 56. Nexus debug port timing1 (continued)
Value No. 8 9 10 11 12
1
Symbol tTCYC TDC tNTDIS, tNTMSS tNTDIH, tNTMSH tJOV CC CC CC CC CC
C
Parameter Min Max -- 60 -- -- 40 100 40 10 5 0
Unit ns % ns ns ns
D TCK Cycle Time3 D TCK Duty Cycle D TDI, TMS Data Setup Time D TDI, TMS Data Hold Time D TCK Low to TDO Data Valid
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 3.0 V to 5.5V, TA = 40 to 105 C, and CL = 50 pF (CL = 30 pF on MCKO), with SRC = 0b11. 2 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3 The system clock frequency needs to be three times faster than the TCK frequency.
1 2 MCKO 3 4 5 MDO MSEO EVTO Output Data Valid
Figure 28. Nexus output timing
TCK 9 8 9
Figure 29. Nexus TCK timing
MPC5606S Microcontroller Data Sheet, Rev. 6 106 Freescale Semiconductor
TCK
10 11
TMS, TDI
12
TDO
Figure 30. Nexus TDI, TMS, TDO timing
3.20.3
Interface to TFT LCD panels
Figure 31 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with positive polarity. The sequence of events for active matrix interface timing is: 1. 2. 3. 4. DCU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, DCU_CLK runs continuously. DCU_HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse. DCU_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. DCU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 107
DCU_VSYNC DCU_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n
DCU_HSYNC DCU_DE 1 DCU_CLK DCU_LD[23:0] 2 3 m-1 m
Figure 31. TFT LCD interface timing overview1
3.20.3.1
Interface to TFT LCD panels--pixel level timings
Figure 32 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DCU_CLK signal (meaning the data and sync signals change on the rising edge) and active-high polarity of the DCU_HSYNC, DCU_VSYNC and DCU_DE signals. The user can select the polarity of the DCU_HSYNC and DCU_VSYNC signals via the SYN_POL register, whether active-high or active-low. The default is active-high. The DCU_DE signal is always active-high. Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are programmed via the DCU Clock Confide Register (DCCR) in the system clock module. The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H and FP_H parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the VSYN_PARA register. Table 57. LCD interface timing parameters--horizontal and vertical
Symbol tPCP tPWH tBPH tFPH tSW tHSP tPWV CC CC CC CC CC CC CC C Parameter Value -- PW_H tPCP BP_H tPCP FP_H tPCP DELTA_X tPCP (PW_H + BP_H + FP_H + DELTA_X ) tPCP PWVtHSP Unit ns ns ns ns ns ns ns
D Display pixel clock period D HSYNC pulse width D HSYNC back porch width D HSYNC front porch width D Screen width D HSYNC (line) period D VSYNC pulse width
1. In Figure 31, the "DCU_LD[23:0]" signal is an aggregation of the DCU's RGB signals--DCU_R[0:7], DCU_G[0:7] and DCU_B[0:7].
MPC5606S Microcontroller Data Sheet, Rev. 6 108 Freescale Semiconductor
Table 57. LCD interface timing parameters--horizontal and vertical (continued)
Symbol tBPV tFPV tSH tVSP CC CC CC CC C Parameter Value BP_V tHSP FP_V tHSP DELTA_Y tHSP (PW_V + BP_V + FP_V + DELTA_Y ) tHSP Unit ns ns ns ns
D VSYNC back porch width D VSYNC front porch width D Screen height D VSYNC (frame) period
tHSP tPWH tPCP tBPH tSW tFPH
Start of line
DCU_CLK
DCU_LD[23:0]
Invalid Data
1
2
3
DELTA_X
Invalid Data
DCU_HSYNC
DCU_DE
Figure 32. Horizontal sync timing
tVSP Start of Frame tPWV tHCP tBPV tSH tFPV
DCU_HSYNC
DCU_LD[23:0] (Line Data)
Invalid Data
1
2
3
DELTA_Y
Invalid Data
DCU_HSYNC
DCU_DE
Figure 33. Vertical sync pulse
3.20.3.2
Interface to TFT LCD panels
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 109
Table 58. TFT LCD interface timing parameters1,2,3,4
Value Symbol tCKP CK tDSU tDHD tCSU tCHD CC CC CC CC CC CC CC CC CC CC CC
1
C D PDI clock period D PDI clock duty cycle D PDI data setup time
Parameter Min 15.25 40 9.5 4.5 9.5 4.5 -- -- -- 2 -- Typ -- -- -- -- -- -- -- -- -- -- -- Max -- 60 -- -- -- -- 6 5.5 5.6 -- 3.7
Unit ns % ns ns ns ns ns ns ns ns ns
D PDI data access hold time D PDI control signal setup time D PDI control signal hold time D TFT interface data valid after pixel clock D TFT interface VSYNC valid after pixel clock D TFT interface DE valid after pixel clock D TFT interface hold time for data and control bits D Relative skew between the data bits
The characteristics in this table are based on the assumption that data is output at positive edge and displays latch data on negative edge 2 Intra bit skew is less than 2 ns 3 Load C = 50 pF for panel frequency up to 20 MHz L 4 Load C = 25 pF for panel frequency from 20 to 32 MHz L
tCHD DCU_HSYNC DCU_VSYNC DCU_DE
tCSU
DCU_CLK tCKH tCKL tDSU tDHD
DCU_LD[23:0]
Figure 34. TFT LCD interface timing parameters
3.20.4
External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) timing
MPC5606S Microcontroller Data Sheet, Rev. 6 110 Freescale Semiconductor
Table 59. IRQ and NMI timing
Value No. 1 2 3
1
Symbol tIPWL tIPWH tICYC CC CC CC
C
Parameter Min Max -- -- -- 200 200
1
Unit ns ns ns
T IRQ/NMI Pulse Width Low T IRQ/NMI Pulse Width High T IRQ/NMI Edge to Edge Time
400
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
1,2 3
1,2
Figure 35. IRQ and NMI timing
3.20.5
eMIOS timing
Table 60. eMIOS timing1
Value
No. 1 2
1
Symbol tMIPW tMOPW CC CC
C
Parameter
Min2 4 1
Unit Max -- -- tCYC tCYC
D eMIOS input pulse width D eMIOS output pulse width
eMIOS timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = 40 to 105 C, and CL = 50 pF with SRC = 0b00 2 There is no limitation on the peripheral for setting the minimum pulse width, the actual width is restricted by the pad delays. Refer to the pad specification section for the details.
3.20.6
FlexCAN timing
The CAN functions are available as TX pins at normal IO pads and as RX pins at the always on domain. There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 111
Table 61. FlexCAN timing1
Value No. 1 2
1
Symbol tCANOV tCANSU CC CC
C
Parameter Min Max 22.48 12.46 -- --
Unit ns ns
D CTNX Output Valid after CLKOUT Rising Edge (Output Delay) D CNRX Input Valid to CLKOUT Rising Edge (Setup Time)
FlexCAN timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = 40 to 105 C, and CL = 50 pF with SRC = 0b00.
MPC5606S Microcontroller Data Sheet, Rev. 6 112 Freescale Semiconductor
3.20.7
Deserial Serial Peripheral Interface (DSPI)
Table 62. DSPI timing1
Value
No. 1 2 3 4 5 6 7
Symbol tSCK tCSC tASC tSDC tA tDIS tSUI CC CC CC CC CC CC CC
C D SCK Cycle TIme2,3 D PCS to SCK Delay D After SCK Delay D SCK Duty Cycle
5 4
Parameter Min 60 20 20 tSCK/2 - 2ns -- -- Max -- -- -- tSCK/2 + 2ns 25 25
Unit ns ns ns ns ns ns
D Slave Access Time (PCSx active to SOUT driven) D Slave SOUT Disable Time (PCSx inactive to SOUT High-Z or invalid) D Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) D Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) D Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) D Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1)
35 5 5 35 -4 10 26 -4 -- -- -- -- -15 5.5 0 -15
-- -- -- -- -- -- -- -- 15 35 30 15 -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8
tHI
CC
9
tSUO
CC
10
tHO
CC
1 2 3 4 5 6
DSPI timing specified at VDDE_x = 3.0 V to 5.5 V, TA = 40 to 105 C, and CL = 50 pF with SRC = 0b11. The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. The actual minimum SCK Cycle Time is limited by pad performance. The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK = 2 and CSSCK = 2 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC] This delay value is corresponding to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 113
2 PCSx 4 SCK Output (CPOL = 0) 4 1
3
SCK Output (CPOL = 1) 7 SIN 8 Data 10 SOUT First Data Data Last Data 9 Last Data
First Data
Note: Numbers in circles refer to values in Table 62.
Figure 36. DSPI classic SPI timing -- master, CPHA = 0
PCSx
SCK Output (CPOL = 0) 8 SCK Output (CPOL = 1) 7 SIN First Data 10 SOUT First Data Data Data Last Data 9 Last Data
Note: Numbers in circles refer to values in Table 62.
Figure 37. DSPI classic SPI timing -- master, CPHA = 1
MPC5606S Microcontroller Data Sheet, Rev. 6 114 Freescale Semiconductor
2 PCSx 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 7 SIN 8 Data 10 Data 9 4
3
6
Last Data
First Data
Last Data
Note: Numbers in circles refer to values in Table 62.
Figure 38. DSPI classic SPI timing -- slave, CPHA = 0
PCSx
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
9 10 First Data 7 8 Data Last Data Data Last Data 6
SIN
First Data
Note: Numbers in circles refer to values in Table 62.
Figure 39. DSPI classic SPI timing -- slave, CPHA = 1
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 115
3 PCSx 4 2 SCK Output (CPOL = 0) SCK Output (CPOL = 1) 7 SIN First Data 10 SOUT First Data Data Data 9 Last Data Last Data 4 1
8
Note: Numbers in circles refer to values in Table 62.
Figure 40. DSPI modified transfer format timing -- master, CPHA = 0
PCSx
SCK Output (CPOL = 0)
SCK Output (CPOL = 1) 7 SIN First Data Data 10 SOUT First Data Data 8
Last Data 9 Last Data
Note: Numbers in circles refer to values in Table 62.
Figure 41. DSPI modified transfer format timing -- master, CPHA = 1
MPC5606S Microcontroller Data Sheet, Rev. 6 116 Freescale Semiconductor
PCSx
2 1
3
SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 7 SIN First Data Data Data 9 10 Last Data 8 Last Data 6 4
Note: Numbers in circles refer to values in Table 62.
Figure 42. DSPI modified transfer format timing -- slave, CPHA = 0
PCSx
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
9 10 First Data 7 8 Data Last Data Data Last Data 6
SIN
First Data
Note: Numbers in circles refer to values in Table 62.
Figure 43. DSPI modified transfer format timing -- slave, CPHA = 1
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 117
3.20.8
I2C timing
Table 63. I2C Input Timing Specifications -- SCL and SDA
Value
No. Symbol C 1 2 4 6 7 8 9
1
Parameter Min Max -- -- -- -- -- -- -- 2 8 0.0 4 0.0 2 2
Unit IP-Bus Cycle1 IP-Bus Cycle1 ns IP-Bus Cycle1 ns IP-Bus Cycle1 IP-Bus Cycle1
-- -- -- -- -- -- --
CC CC CC CC CC CC CC
D Start condition hold time D Clock low time D Data hold time D Clock high time D Data setup time D Start condition setup time (for repeated start condition only) D Stop condition setup time
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
Table 64. I2C Output Timing Specifications -- SCL and SDA
Value No. Symbol C 11 21 33 4
1
Parameter Min Max 6 10 -- 7 -- 10 2 20 10 -- -- 99.6 -- 99.5 -- -- -- --
Unit IP-Bus Cycle2 IP-Bus Cycle1 ns IP-Bus Cycle1 ns IP-Bus Cycle1 IP-Bus Cycle1 IP-Bus Cycle1 IP-Bus Cycle1
-- -- -- -- -- -- -- -- --
CC CC CC CC CC CC CC CC CC
D Start condition hold time D Clock low time D SCL/SDA rise time D Data hold time D SCL/SDA fall time D Clock high time D Data setup time D Start condition setup time (for repeated start condition only) D Stop condition setup time
51 61 71 81 91
1
Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device 3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
MPC5606S Microcontroller Data Sheet, Rev. 6 118 Freescale Semiconductor
2
6
5
SCL 3 1 SDA 4
7
8
9
Figure 44. I2C input/output timing
3.20.9
* *
QuadSPI timing
The following notes apply to Table 65: All data are based on a negative edge data launch from MPC5606S and a positive edge data capture as shown in the timing diagrams. Typical values are provided from center-split material at 25 C and 3.3 V. Minimum and maximum values are from a temperature variation of -45 C to 105 C and the following supply conditions: -- IO voltage: 3.2 V, core supply: 1.2 V -- IO voltage: 3.6 V, core supply: 1.2 V All measurements are taken at 70% of VDDE levels for clock pin and 50% of VDDE level for data pins. Timings correspond to QSPI_SMPR = 0x0000_000x. See the MPC5606S Microcontroller Reference Manual for details. A negative value of hold is an indicaPLtion of pad delay on the clock pad (delay between the edge capturing data inside the device and the edge appearing at the pin). Values are with a load of 15pF on the output pins. Table 65. QuadSPI timing
Value Symbol tCQ tS tH tR tF CC CC CC CC CC C T Clock to Q delay T Setup time for incoming data T Hold time requirement for incoming data T Clock pad rise time T Clock pad fall time Parameter Min 1.60 6.1 -12.5 0.4 0.3 Typ 2.4 9.4 -8.5 0.6 0.5 Max 5.33 12.1 -7.5 1.0 0.9 ns ns ns ns ns Unit
* * * *
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 119
1
Tcq
SCK DO
Figure 45. QuadSPI output timing diagram
1
Tcq 2 3
4
5
6
7
8
SCK DO Ts Th DI 1. 2. 3. 4. 5. 6. 7. 8. Last address out Address captured at flash Data out from flash Ideal data capture edge Delayed data capture edge with QSPI_SMPR=0x0000_000x Delayed data capture edge with QSPI_SMPR=0x0000_002x Delayed data capture edge with QSPI_SMPR=0x0000_004x Delayed data capture edge with QSPI_SMPR=0x0000_006x
Figure 46. QuadSPI input timing diagram The clock profile in Figure 47 is measured at 30% to 70% levels of VDDE.
MPC5606S Microcontroller Data Sheet, Rev. 6 120 Freescale Semiconductor
tr
70%
tf
VDDE
30%
SCK
Figure 47. QuadSPI clock profile
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 121
4
4.1
Package mechanical data
144 LQFP
MPC5606S Microcontroller Data Sheet, Rev. 6 122 Freescale Semiconductor
Figure 48. LQFP144 mechanical drawing (Part 1 of 3)
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 123
Figure 49. LQFP144 mechanical drawing (Part 2 of 3)
MPC5606S Microcontroller Data Sheet, Rev. 6 124 Freescale Semiconductor
Figure 50. LQFP144 mechanical drawing (Part 3 of 3)
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 125
4.2
176 LQFP
Figure 51. LQFP176 mechanical drawing (Part 1 of 3)
MPC5606S Microcontroller Data Sheet, Rev. 6 126 Freescale Semiconductor
Figure 52. LQFP176 mechanical drawing (Part 2 of 3)
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 127
Figure 53. LQFP176 mechanical drawing (Part 3 of 3)
MPC5606S Microcontroller Data Sheet, Rev. 6 128 Freescale Semiconductor
5
Ordering information
Example production code: Qualification status Power Architecture core Automotive platform Core Version Flash Size (core dependent) Product Fab, mask version, mask set indicator Temperature options Package option Speed Shipping method M PC 56 0 6 S F0A V LU 6 R
Qualification status M = General market qualified P = Engineering samples S = Automotive qualified Automotive platform 56 = Power Architecture in 90nm Core version 0 = e200z0 Flash memory size (z0 core) 2 = 256 KB 4 = 512 KB 6 = 1 MB
Product version S = Cluster Fab, mask version, mask set indicator (only used for SPC part numbers) F = ATMC fab 0 = Maskset version (0, 1, etc.) A = Maskset indicator: Blank: First production maskset A: Second production maskset B: Third production maskset ...
Temperature spec. C = -40 to 85 C V = -40 to 105 C Package option LQ = 144 LQFP LU = 176 LQFP1 MG = 208 MAPBGA2 Speed 6 = 64 MHz Shipping method Blank = Tray R = Tape and reel
Example custom-build code: Custom device prefix 6-digit number Fields as for production chips (see above)
SC 123456
V
LU
6
R
1 2
The 176-pin package is available only for chips with 1 MB flash memory. 208 MAPBGA available only as development package for Nexus2+, and will not be qualified for production
Figure 54. Commercial product code structure
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 129
6
Revision history
Table 66. Document revision history
Revision 1 2 Date 10-2008 Initial release. Substantive changes
18 Aug 2009 Editorial changes and improvements. Harmonized oscillator naming throughout document Section 1.5, "MPC5606S features: Updated description of ADC channels Table 2: Changed max number of GPIOs from 132 to 133 for LQFP176 Table 3: Corrected "Peripheral interrupt timer (PIT)" to "Periodic interrupt timer (PIT)" Figure 2: - Added GPIOs to pin function names - Changed function of pin 32: was NC--is VREG_BYPASS - Pin 55: Changed XTAL32 to OSC32K_XTAL - Pin 56: Changed EXTAL32 to OSC32K_EXTAL Figure 5: - Added GPIOs to pin function names - Changed function of pin 32: was NC--is VREG_BYPASS - Pin 71: Changed XTAL32 to OSC32K_XTAL - Pin 72: Changed EXTAL32 to OSC32K_EXTAL Table 6: - Removed pins EXTAL32, XTAL32 and NMI - Updated VRC_CTL I/O direction and pad type Table 7: - Replaced "A" with "I" in pad type column - Modified table footnote 3 to replace pad type "A" definition with pad type "I" definition Table 8: Moved MA[0:2] to follow AN[0:15] Added Section 3.2, "Parameter classification and added classification tags to electrical characteristics tables where appropriate Added Section 3.3, "NVUSRO register Table 14: Removed ESDHBM Table 17: Merged 144- and 176-pin LQFP characteristics into single table Added Section 3.6, "Electromagnetic compatibility (EMC) characteristics Table 26: Removed "TA = 25 C, after trimming" from conditions for VPORH, VLVDH3V and VLVDH5V Table 27: - Changed TA = 40 to 125 C to TA = 40 to 105 C in note 1 - Added STANDBY1 and STANDBY2 mode current characteristics Figure 12: Updated to reference GPDI register and values for bit PDI Section 3.8.1, "I/O pad types: Corrected "four main I/O pad types" to read "three main I/O pad types" Section 3.8.3, "I/O output DC characteristics: Replaced ipp_hve with PAD3V5V
MPC5606S Microcontroller Data Sheet, Rev. 6 130 Freescale Semiconductor
Table 66. Document revision history
Revision 2 (continued) Date Substantive changes
18 Aug 2009 Table 37: (continued) - IRMSMED: Replaced SLOW with MEDIUM in parameter column - IRMSFST: Replaced SLOW with FAST in parameter column Section 3.8.4, "I/O pad current specification: Replaced ipp_hve with PAD3V5V Section 3.10, "RESET electrical characteristics: Replaced ipp_hve with PAD3V5V Updated Figure 13 Updated Figure 16 Updated Figure 18 Section 3.19, "Pad AC specifications: Replaced IPP_HVE with PAD3V5V Table 45: Added rows IFIRCSTOP and tFIRCSU Table 46: - Added rows tSIRCSU and SIRCTRIM - Updated conditions for SIRCVAR Added Table 42 "ADC input leakage current" Table 50: Updated TUEp and TUEx Table 7: Modified PC[0] to PC[9]: - I/O direction: was I, is I/O - pad type: was I, is S Table 50: Updated values for `Input current injection' Section 3.20.3, "Interface to TFT LCD panels: Modified description of event No. 1 in sequence for active matrix interface timing Table 57: Removed value for Display pixel clock period Table 53: Removed duplicated row for part number MPC5604SEMLQ Section 2.4.2, "Voltage Supply Pins": Added preferred power up sequence. Section 2.9, "Port pin summary": Changed reset configuration on ADC pins. Section 3, "Electrical characteristics: Made updates to data. All data is still considered preliminary. Section 3.7.1, "Voltage regulator electrical characteristics": Added lower power voltage regulator and ultra-low power voltage regulator characteristics.
3 4
-- --
Not released; no substantive changes between Rev. 2 and Rev. 3. Not released; no substantive changes between Rev. 3 and Rev. 4.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 131
Table 66. Document revision history
Revision 5 Date Substantive changes
1 Sep 2010 Editorial changes and improvements. Replaced "validation" with "characterization" throughout. Added an entry for Rev. 3 to this table. In the block diagram, in the SXOSC block, changed "32 kHz" to "32 KHz". Revised the feature section and added the "Feature details" subsection. Renamed the analog pins (were AN..., are ANS...) throughout. Changed several pin names that contained _A, _B, _C, ... to contain _0, _1, _2, ... throughout. Changed the PCS and oscillator pin names throughout. Revised the feature section and added the "Feature details" subsection. Deleted the out-of-date "Block summary" section. In the 144-pin pinout: * For pin 122, changed PCS_B1 to PCS1_1. * For pin 123, changed PCS_B0 to PCS0_1. In the "144 LQFP package pinout" section, added pinouts for the chips with 512 KB and 256 KB flash memory. In the 176-pin pinout: * For pin 152, changed PCS_B1 to PCS1_1. * For pin 153, changed PCS_B0 to PCS0_1. Revised the "Pad configuration during reset phases", "Voltage supply pins", "Pad types", "System pins", and "Nexus pins" sections. Changed several module names and abbreviations to be consistent with the official module names and abbreviations. In the "Voltage supply pin descriptions" table, revised the entry for VDD12. In the "Debug pin descriptions" table, changed pad type M to pad type M1. In the "Pad types" section, changed "registers in the device reference manual" to "registers in the SIUL chapter of the device reference manual". Changed the name of the port-pin summary section (was "Functional ports A, B, C, D, E, F, G, H, I, J, K", is "Port pin summary"). In the "Signal details" section: * Renamed the analog pins (were AN..., are ANS...). * Added "ANS[0:15] connect to ATD channels [32:47]" to the ANS signal description. * Added "The available 8 multiplexed channels connect to ATD channels [64:71]" to the MA signal description. * Deleted "when high; otherwise low to allow a subframe display for pixels" from the DCU_DE description. * Changed the description for DCU_TAG, PDI_PCLK, TXD_A, and SSD signals. * Added QuadSPI signals. * Deleted "For valid Pixel Data this is high, otherwise low" from the PDI_DE description. * Changed several pin names that contained _A, _B, _C, ... to contain _0, _1, _2, ... In the "Port pin summary" table: * Changed the pad type for PC[0]--PC[9] (was S, is J). * Moved the AN[0]--AN[15] entries from the "Function" column to the "Special function" column. * Moved the OSC32K_EXTAL and OSC32K_XTAL entries from the "Function" column to the "Special function" column. * Added alternate function names and clarifying footnotes to the PF[11]--PF[14] entries. * Added new information on pad types (including splitting up the existing M pads into two categories, M1 and M2). * Added a footnote to the "Special function" column title.
MPC5606S Microcontroller Data Sheet, Rev. 6 132 Freescale Semiconductor
Table 66. Document revision history
Revision 5 (continued) Date Substantive changes
1 Sep 2010 Added a footnote to the "Pad type description" table. (continued) In the "Pad type description" table: * Revised the entry for SMD. * Revised the description for the J and M2 pad types. Revised the entry for VSSPLL in the "Absolute maximum ratings" and "Recommended operating conditions" table. Changed the max value for VDDPLL (was 1.32 V, is 1.4 V) in several tables. Added the "Connecting power supply pins: What to do and what not to do" section. In the "Recommended operating conditions" table, changed the note to state "Maximum slew..." instead of "Minimum slew...". In footnote 2 of the "Recommended operating conditions" table, changed "200 F capacitance must be connected between VDDR and VSS12" to "10 F capacitance must be connected between VDDR and VSS12.". In the "Recommended operating conditions" section, added a caution on which voltages must be the same. In the "Recommended operating conditions (3.3 V)" table: * Revised the footnote affecting VDD12/VSS12 supply capacitances. * Deleted footnote 9. * Deleted the entries for VDDPLL and VDD12. In the "Recommended operating conditions (5.0 V)" table: * Changed the footnote text "200 F capacitance must be connected between VDDR and VSS12" to "10 F capacitance must be connected between VDDR and VSS12" and revised the footnote affecting VDD12/VSS12 supply capacitances. * Added a specification for TVDD. * Deleted the entries for VDDPLL and VDD12. Revised the "EMC requirements on board" section. Added meaningful values to the "EMI testing specifications" table. In the "ESD absolute maximum ratings" table, added a specification for VESD(MM). Deleted the empty "DC Electrical Characteristics" section. In the "I/O pad types" section, added an entry for SMD pads. Added SMC pad electrical characteristics. Revised the "Voltage regulator electrical characteristics" section. Revised the "Low-power voltage regulator electrical characteristics" table. Revised the "Ultra-low power voltage regulator electrical characteristics" table. Revised the "Low voltage monitor electrical characteristics" table. Added the "Recommended power-up and power-down order" section. Added the "Power-up inrush current profile" section. Added the "HPREG load regulation characteristics" section. Revised the "DC electrical characteristics" table. Replaced all values for "STANDBY mode current". Revised the "I/O pad types" section. In the "I/O input DC electrical characteristics" table: * Changed the specifications for ILKG (was min = <1 A, is min = -1 A; was max = --, is max = 1 A). * Added an entry for RON. Revised the "I/O output DC characteristics" section. Revised the "MEDIUM configuration output buffer electrical characteristics" table. Revised the "SMD pad electrical characteristics" table and changed its name (is "SMC pad..."). In the "SMC pad electrical characteristics" table, changed RDSOH to RDSONH and RDSOL to RDSONL. Moved the IMAX specification from the "SMC pad electrical characteristics" table to the "Absolute maximum ratings" table.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 133
Table 66. Document revision history
Revision 5 (continued) Date Substantive changes
1 Sep 2010 Added the "SMC pad delays" table. (continued) Added the "SSD specifications" section. In the "I/O consumption" table, added a specification for IDDMxAVG. Revised the "Fast external crystal oscillator (4-16 MHz) electrical characteristics" table. In the "Slow external crystal oscillator (32 kHz) electrical characteristics" figure, changed VOSC32K_XTAL to VSXOSC_XTAL. In footnote 2 of the "FMPLL electrical characteristics" table, changed "fCPU 64 MHz can be achieved only at up to 105 C" to "fCPU 64 MHz can be achieved only at temperatures up to 105 C with a maximum FM depth of 2%". In the first "Crystal oscillator and resonator connection scheme" figure: * Swapped "XTAL" and "EXTAL". * Deleted RP. In the second "Crystal oscillator and resonator connection scheme" figure, deleted RF. Added the "Crystal description" table. In the "Fast internal RC oscillator (16 MHz) electrical characteristics" table: * Changed the conditions for FIRCVAR (was "TA = -25 C", is "TA = -40 to 105 C, trimmed"), removed the associated footnote, and changed the associated guarantee method (was P, is C). * Changed the max specification for IFIRCPWD (was 10 A, is 1 A). Added the "Resonator description" table. In the "Fast external crystal oscillator (4 to 16 MHz) electrical characteristics" table, changed footnote 1 (was "... to 125 C", is "... to 105 C"). In the "Slow external crystal oscillator" section, changed "32 kHz" to "32 KHz". In the "Slow external crystal oscillator (32 KHz) electrical characteristics" table, added a footnote to the start-up timing specification. In the "Slow internal RC oscillator (128 KHz) electrical characteristics" table: * Changed the condition for SIRCVAR (was --, is "Trimmed") and the associated guarantee method (was P, is C). * Changed the guarantee method for fSIRC (was P, is C). Revised the "Program and erase specifications" table. In the "Flash memory read access timing" table, changed footnote 1 (was "... to 125 C", is "... to 105 C"). Revised the "Flash module life" table. Added flash read access timing characteristics. In the "ADC conversion characteristics" table: * Deleted the entry for TUEp (precision channels are not implemented on this device). * Changed the specification for INL (was min = -1.5 LSB and max = 1.5 LSB, is min = max = 2.5 LSB). * Revised the entry for IINJ (was 10 mA, is 5 mA). * Changed the max specifications for RSW1 (was 3 k, is 1 k) and for RSW2 (was 2 k, is 1 k). Added the "LCD driver electrical characteristics" section. Revised the table titles in the "Pad AC specifications" section. Added the "QuadSPI timing" section. Revised the "JTAG interface timing" table. Revised the "Nexus debug port timing" table. Renamed the "Interface to TFT LCD panels--access level" section (is "Interface to TFT LCD panels") and revised the table (title and contents) within it. In the "DSPI timing" table, added a min specification for tCSC (is 20 ns). In the DSPI section, added a note (referring to the "DSPI timing" table) to each timing diagram. Revised the "Ordering information" section.
MPC5606S Microcontroller Data Sheet, Rev. 6 134 Freescale Semiconductor
Table 66. Document revision history
Revision 6 Date Substantive changes
14 Jan 2011 Editorial changes and improvements. Swapped XTAL and EXTAL pins for the 208-pin BGA package and throughout. In the "Pinout and signal descriptions" section, changed WARNING labels to CAUTION labels. Updated the "Absolute maximum ratings" and "Recommended operating conditions" tables. Added footnote reference to Vss12 in "Recommended operating conditions (3.3 V)" table. Updated the "Connecting power supply pins" section. Removed footnote regarding characterization in the "Thermal characteristics" table. Updated the VDD12/VDDPLL operating voltages in the "Electromagnetic interference" table. Added typical values and updated the "Voltage regulator electrical characteristics", "Low-power voltage regulator electrical characteristics", and "Ultra-low-power voltage regulator electrical characteristics" tables. Updated classifications and values in the "Low voltage monitor electrical characteristics" table. Made major modifications and updates to the "DC electrical characteristics" table. Made major modifications and updates to the "I/O input DC electrical characteristics" table. Made major modifications and updates to the "I/O pull-up/pull-down DC electrical characteristics" table. Changed "SMC" pads to "SMD" pads throughout. Made updates to the "SMD pad electrical characteristics" table. Added run current during RESET to the "Reset electrical characteristics" table. Updated the FMPLL jitter (peak to peak) specification in the "FMPLL electrical characteristics" table. Updated fFIRC and tFIRCSU in the "Fast internal RC oscillator (16 MHz) electrical characteristics" table. Updated fSIRC and tSIRCSU in the "Slow internal RC oscillator (128 KHz) electrical characteristics" table. Removed "symmetric" pad type from the "Pad AC specifications (5.0 V, PAD3V5V = 0)" table. Removed "symmetric" pad type from the "Pad AC specifications (3.3 V, PAD3V5V = 1)" table. Updated VDD12 post-trimming minimum value in the "Low-power voltage regulator electrical characteristics" table. Updated VDD12 post-trimming minimum value in the "Ultra-low-power voltage regulator electrical characteristics" table. Updated VLVDLVCORH maximum value in the "Low voltage monitor electrical characteristics" table. Updated VLVDLVCORL minimum value in the "Low voltage monitor electrical characteristics" table. Updated value of VDD12/VDDPLL operating voltages in the "Input DC electrical characteristics" table. Corrected erroneous value of ILKG (105C case) in the "Input DC electrical characteristics" table.
MPC5606S Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 135
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MPC5606S Microcontroller Data Sheet, Rev. 6 136 Freescale Semiconductor

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